5962G0254301VXC View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

5962G0254301VXC

RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Low Voltage Transceiver

Aeroflex UTMC 

UT54ACS162245S

RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Low Voltage Transceiver

Datasheet

March 12, 2003

FEATURES

• Voltage translation

- 3.3V bus to 2.5V bus

- 2.5V bus to 3.3V bus

• Cold sparing all pins

• 0.25µ Commercial RadHardTM CMOS

- Total dose: 300Krad(Si) and 1Mrad(Si)

- Single Event Latchup immune

• High speed, low power consumption

• Schmitt trigger inputs to filter noisy signals

• Cold and Warm Spare - all outputs

• Available QML Q or V processes

• Standard Microcircuit Drawing 5962-02543

• Package:

- 48-lead flatpack, 25 mil pitch (.390 x .640)

DESCRIPTION

The 16-bit wide UT54ACS162245S MultiPurpose low voltage

transceiver is built using Aeroflex UTMC’s Commercial

RadHardTM epitaxial CMOS technology and is ideal for space

applications. This high speed, low power UT54ACS162245S

low voltage transceiver is designed to perform multiple func-

tions including: asynchronous two-way communication,

Schmitt input buffering, voltage translation, warm and cold

sparing. With VDD equal to zero volts, the UT54ACS162245S

outputs and inputs present a minimum impedance of 1MΩ mak-

ing it ideal for "cold spare" applications. Balanced outputs and

low "on" output impedance make the UT54ACS162245S well

suited for driving high capacitance loads and low impedance

backplanes. The UT54ACS162245S enables system designers

to interface 2.5 volt CMOS compatible components with 3.3

volt CMOS components. For voltage translation, the A port in-

terfaces with the 2.5 volt bus; the B port interfaces with the 3.3

volt bus. The direction control (DIRx) controls the direction of

data flow. The output enable ( OEx) overrides the direction con-

trol and disables both ports. These signals can be driven from

either port A or B. The direction and output enable controls

operate these devices as either two independent 8-bit transceiv-

ers or one 16-bit transceiver.

LOGIC SYMBOL

O E1 (48)

O E2 (25)

(1)

DIR1

G1

G2

2EN1 (BA)

2EN2 (AB)

1EN1 (BA)

1EN2 (AB)

(47)

1A1

(46)

1A2

(44)

1A3

(43)

1A4

(41)

1A5

(40)

1A6

(38)

1A7

(37)

1A8

(36)

2A1

(35)

2A2

(33)

2A3

(32)

2A4

(30)

2A5

(29)

2A6

(27)

2A7

(26)

2A8

11

12

21

22

(24)

DIR2

(2)

1B1

(3)

1B2

(5)

1B3

(6)

1B4

(8)

1B5

(9)

1B6

(11)

1B7

(12)

(13) 1B8

2B1

(14)

2B2

(16)

2B3

(17)

2B4

(19)

2B5

(20)

2B6

(22)

2B7

(23)

2B8

PIN DESCRIPTION

Pin Names

Description

O Ex

Output Enable Input (Active Low)

DIRx

Direction Control Inputs

xAx

Side A Inputs or 3-State Outputs (2.5V Port)

xBx

Side B Inputs or 3-State Outputs (3.3V Port)

1

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