HD404328H View Datasheet(PDF) - Hitachi -> Renesas Electronics

Part Name

Description

Manufacturer

HD404328H

4-Bit Microcontroller

Hitachi -> Renesas Electronics 

HD404328 Series

RAM Memory Map

The MPU contains a 280-digit × 4-bit (HD404324, HD404324U, HD404326, HD404326U, HD404328,

HD404328U) or 536-digit × 4-bit (HD4074329, HD4074329U) RAM area consisting of a data area and a

stack area. In addition, interrupt control bits and special registers are mapped onto the same RAM memory

space outside this area. The RAM memory map is shown in figure 2 and described below.

0

$000

RAM-mapped registers

63

(64 digits)

$03F

64

$040

Memory registers (MR)

79

(16 digits)

$04F

80

$050

LCD display area

103

(24 digits)

$067

104

$068

Not used

111

$06F

112

Data

$070

287

(176 digits)

$11F

288

$120

Data

(256 digits)

543

$21F

544

$220

Not used

959

960

1023

Stack

(64 digits)

$3BF

$3C0

$3FF

Shaded area can only be

used by the HD4074329, and

HD4074329U

R: Read only

W: Write only

R/W: Read/write

Note: * Two registers mapped on the

same area

Timer/event counter B, lower

(TCBL)

Timer/event counter B, upper

(TCBU)

Timer counter C, lower

(TCCL)

Timer counter C, upper

(TCCU)

0

$000

1

2

Interrupt control bits area

$001

$002

3

$003

4 Port mode register A (PMRA) W $004

5 Serial mode register

(SMR) W $005

6 Serial data register, lower (SRL) R/W $006

7 Serial data register, upper (SRU) R/W $007

8 Timer mode register A (TMA) W $008

9 Timer mode register B (TMB) W $009

10

11

*Timer B

(TCBL/TLRL) R/W $00A

(TCBU/TLRU) R/W $00B

12 Miscellaneous register

(MIS) W $00C

13 Timer mode register C (TMC) W $00D

14

15 *Timer C

(TCCL/TCRL) R/W $00E

(TCCU/TCRU) R/W $00F

16 Interrupt mode register (IMR) W $010

17 Port mode register B (PMRB) W $011

18 Port mode register C (PMRC) W $012

19 LCD control register

(LCR) W $013

20 LCD mode register

(LMR) W $014

21 LCD output register

(LOR) W $015

22 A/D mode register

(AMR) W $016

23 A/D data register, lower (ADRL) R $017

24 A/D data register, upper (ADRU) R $018

Not used

32

$020

35

Register flag area

$023

Not used

48 Port R0 DCR

49 Port R1 DCR

50 Port R2 DCR

51 Port R3 DCR

52 Port R4 DCR

53 Port R5 DCR

(DCR0) W $030

(DCR1) W $031

(DCR2) W $032

(DCR3) W $033

(DCR4) W $034

(DCR5) W $035

Not used

59 Port D0–D3 DCR

(DCRB) W $03B

60 Port D4–D7 DCR

(DCRC) W $03C

61 Port D8 DCR

(DCRD) W $03D

62

63

Not used

$03E

$03F

R

Timer load register B, lower

(TLRL)

W $00A

R

Timer load register B, upper

(TLRU)

W $00B

R

Timer load register C, lower

(TCRL)

W $00E

R

Timer load register C, upper

(TCRU)

W $00F

Figure 2 RAM Memory Map

9

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