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HD404328U View Datasheet(PDF) - Hitachi -> Renesas Electronics

Part Name
Description
Manufacturer
HD404328U
Hitachi
Hitachi -> Renesas Electronics Hitachi
HD404328U Datasheet PDF : 94 Pages
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HD404328 Series
D Port (D0–D10): Consist of 9 input/output pins and 2 input pins. Pins D0–D7 are high-current I/O pins, D8
is an ordinary input/output pin, and D9 and D10 are input-only pins. These pins are set by the SED and
SEDD instructions, reset by the RED and REDD instructions, and tested by the TD and TDD instructions.
The operating modes of D8–D10 are set by bits 2 and 3 of port mode register A (PMRA) and bits 0 and 1 of
port mode register B (PMRB), as shown in figure 24. The on/off status of the output buffer is controlled by
D port data control registers (DCRB, DCRC, and DCRD) that are mapped to memory addresses.
R Ports: Accessed in 4-bit units. Data is input to these ports by the LAR and LBR instructions and output
from them by the LRA and LRB instructions. The on/off status of the output buffers of the R ports are
controlled by R port data control registers (DCR0–DCR5) that are mapped to memory addresses.
Pins R10–R13 are multiplexed with pins SCK, SI, SO, and BUZZ, respectively. The operating modes of
these pins are controlled by bit 3 of the serial mode register (SMR), bits 1 and 0 of port mode register A
(PMRA), and bit 2 of port mode register C (PMRC), as shown in figure 24.
Ports R2–R5 are multiplexed with SEG1–SEG16. The functions of these pins must be specified by the
LCD output register (LOR: $015).
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