5962G9855202QXC View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

5962G9855202QXC

RadHard MicroController

Aeroflex UTMC 

The UT69R000 begins operation by first generating an address

on the instruction port; valid data (instruction) is then latched

into the Primary Instruction Register (PIR). After the machine

stores the instruction in the PIR, the machine begins execution

of the instruction in the Instruction Register (IR). If the present

instruction in the IR requires only internal processing, the

machine does not exercise the data bus. If the machine needs

additional data to complete the instruction the machine begins

arbitration for the data port.

Data port arbitration begins with the machine asserting the Bus

Request (BRQ) signal. The machine samples the Bus Grant

(BGNT) and Bus Busy (BUSY) signals on the falling edge of

the clock (OSCIN). When the machine detects that the previous

bus controller has relinquished control of the bus, the machine

generates a Bus Grant Acknowledge (BGACK) signal

signifying that it has taken control of the bus (i.e., data port).

After the UT69R000 takes control of the bus, it generates valid

address and data information. If the machine is interfacing to

slow memory or other peripheral devices that require long

memory-access times, the Data Transfer Acknowledge

(DTACK) signal extends the memory cycle time. By holding

off the assertion of DTACK, the slow device lengthens the

memory cycle until it can provide data for the machine.

The UT69R000 controls the vectoring and prioritizing of

interrupt service. Internal logic selects one of 15 interrupt

vectors, each interrupt vector is allocated four memory

locations. Use the four memory locations to store return from

interrupt service address information along with the interrupt

service routine’s location. The UT69R000 controls prioritizing

of coincident interrupts.

Perform UART control and maintenance via input/output

commands OTR and INR. These commands allow the

programmer to read UART status, and error information, as

well as upload and download information to the receive and

transmit buffers respectively.

Figure 4 shows an example of a system configuration.

INSTRUCTION MEMORY

CAN ONLY BE ACCESSED

BY THE UT69R000

INSTRUCTION

MEMORY

16

BRQ

BGNT

BUSY

BGACK

INSTRUCTION

DATA

1M X 16

(MAX)

20

INSTRUCTION

ADD OP ADD

OE OP DATA

WE CONTROL

4

BUS

ARBITER

DMA

DEVICE

#1

1553

I/F

16

16

6

INTERNALLY

PULLED LOW

USER-

DEFINED

8

SYSTEM

INTERRUPTS

NUI3

UT69R000

UART

I/F

GENERAL

PURPOSE

MEMORY

I/O

DEVICE #1

X

C

V

SERIAL I/O

R

Figure 4. The UT69R000 Example System Configuration

DMA

DEVICE

#2

I/O

DEVICE #2

5

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