5962F9855201VXX View Datasheet(PDF) - Aeroflex UTMC
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5962F9855201VXX Datasheet PDF : 62 Pages
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1.0 Introduction
The UT69R000 is a radiation-hardened high-performance
microcontroller designed, manufactured, and tested to meet
rigorous radiation environments. UTMC designed and
implemented the UT69R000 using an advanced radiation-
hardened twin-well CMOS process. The combination of
radiation-hardness, high throughput, and low power
consumption makes the UT69R000 ideal for high-speed
systems in satellites, missiles, and avionics applications.
1.1 General Description
The UT69R000 is a versatile microcontroller designed to meet
real-time control type applications. Support functions often
found external to a microprocessor are integrated within the
microcontroller. Functions include UART, interval timers, 10
external interrupt vectors, and a 8-bit output discrete bus.
The UT69R000 core (machine) is a two port microcontroller
that accesses instructions from a 1M x 16 instruction port; a
second port (64K x 16 data port) is available for data storage.
Data transfer acknowledge allows the addition of wait states
on the data port. The machine performs overlapping fetches
and executes speeding instruction throughput. A 12 MHz
operating clock frequency provides up to 6 MIPS of
throughput. A later section of this data sheet expands on this
concept.
The UT69R000 architecture is based on 20 16-bit general
purpose registers providing, the programmer with extensive
register support. The UT69R000’s flexibility is enhanced by
the concatenation of 16-bit registers into 32-bit registers. In
addition, all registers are available for use as either the source
or destination for any register operation.
All UT69R000 circuitry is of static design. Internal registers,
counters, and latches do not require refresh as with dynamic
circuit design. Therefore the UT69R000 can operate from DC
to the upper frequency limit of 16 MHz. This type of operation
is especially useful in power critical applications such as
satellites.
The UT69R000 fully supports multiprocessor systems, DMA,
and complex bus arbitration. Bus control passes among bus
masters operating on the same bus. The bus master can be one
of several UT69R000s or any other device requiring DMA.
The UT69R000 supports 15 levels of vectored interrupts. Ten
of these are external interrupts, all of which are user-definable.
All interrupts are serviced in order of priority.
The UT69R000’s three basic instruction formats support 16-
bit and 32-bit instruction. The formats are Register-to-Register,
Register-to-Literal, and Register-to-Long-Immediate
instructions.
Figure 3 shows the UT69R000’s general system architecture.
1.2 General Operation
The UT69R000 reduced instruction set consists of 35 separate
instructions. Most of these instructions execute in two clock
cycles providing high-throughput. The UT69R000 has a
Harvard architecture which incorporates two address and two
data buses. One set of address and data buses interface with
instruction memory (instruction port) and the other interfaces
with data memory (data port). The instruction port consists of
a 20-bit address bus and 16-bit data bus. The maximum
program length of any program is 1 mega-word. The data port
consists of a 16-bit address and data bus, allowing access to
64K x 16 of data storage.
The instruction port is dedicated to the storage of instruction
code; however , two instructions exist that allow the instruction
port manipulation by the machine. These instructions are the
Load Register from Instruction Memory (LRI) and Store
Register to Instruction Memory (STRI).
INSTRUCTION
MEMORY
INSTRUCTION
DATA
16
20
INSTRUCTION
ADDRESS
UT69R000
DATA
16
CONTROL
ADDRESS
16
Figure 3. UT69R000 General System Architecture
DATA
MEMORY
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