59629855201VZC View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

59629855201VZC

RadHard MicroController

Aeroflex UTMC 

UART CONTROL/TIMER CLOCK

Continued from page 41

PIN NAME

TIMCLK

DI2

TEST

DI1

PIN NUMBER

FLTPK PGA

53

L13

TYPE

TI

ACTIVE

--

48

N12 TDI

--

46

P13 TUI

AL

49

N13 TDI

--

DESCRIPTION

Timer Clock. This 12 MHz clock input generates the baud

rate for the UT69R000’s internal UART. The input also

provides the clock for the UT69R000’s two internal timers

(TIMER A and TIMER B).

Discrete Input 2. Asserting this input sets bit 3 in the

System Status Register Bit 3 is read with the Input Register

Instruction (INR). Tied to an internal pull-down resistor.

(asynchronous input).

Test (Input). Asserting this input places the UT69R000

into a test mode. In this mode, all the UT69R000’s

outputs, except OSCOUT and SYSCLK, enter a high-

impedance state. When using TEST, the UT69R000

must have a MRST. MRST must be held active for at

least one SYSCLK period after TEST is deasserted to

assure proper operation (see figure 41b). TEST is tied

to an internal pull-up resistor.

Discrete Input 1. Asserting this input sets bit 8 in the

System Status Register. Bit 8 is read with the Input

Register Instruction (INR). Tie to a internal pull-down

resistor. (asynschronous input).

PROCESSOR MODE

PIN NAME

OD0

OD1

OD2

OD3

OD4

OD5

OD6

OD7

PIN NUMBER

FLTPK PGA

104

B7

105

B6

106

C6

107

A5

108

A4

109

A3

110

B4

111

C5

TYPE

TTO

ACTIVE

--

DESCRIPTION

Output Discrete Bus (OD(7:0)). These outputs reflect

the status of bits 0 through 7 of the Status/Output

Discrete Register. Write to this register using Output

Register Instruction (OTR). Outputs enter a high-

impedance state when the UT69R000 is placed in the

test mode (TEST = 0).

42

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