5962F9855201QXC View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

5962F9855201QXC

RadHard MicroController

Aeroflex UTMC 

INTERRUPT

NUMBER

0

(Highest

Priority)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

(Lowest

Priority)

Table 1. Interrupt Definitions

DESCRIPTION

Power-Down Interrupt.Cannot be masked or disabled.

Machine Error. Cannot bedisabled.

INT0. External user interrupt.

Software interrupt (USR3)

Fixed-point overflow.(V bit)

Software interrupt (USR2)

Software interrupt (USR1)

Timer A (If implemented).

INT1. External user interrupt.

Timer B (If implemented).

INT2. External user interrupt.

INT3. External user interrupt.

INT5. External user interrupt.

INT4. External user interrupt.

INT6. External user interrupt.

Useful in the control of external subsystem hardware, the

output discrete function is fully static and remains unchanged

until rewritten. Outputs can drive standard (i.e., sink or source)

TTL loads. These outputs three-state on the assertion of the

TEST input pin. Figure 23 shows the timing relationships for

a write to the output discrete bus.

5.2 Discrete Inputs

Status register bits DI1 and DI2, bits 8 and 3 respectively,

reflect the stimulus applied to the input pins. In a system

application the software would make decisions based on the

state (i.e., logic one or zero) of either or both of these bits. The

system software would poll the Status Register by executing

an Input Register Instruction INR Rd,SW; the software then

proceeds to perform a test bit on the appropriate bit (i.e., 3 or

8). The result of the test bit determines the next task performed

by the software. Section 7.0 discusses an example of using a

discrete input to control program for entering the monitor

program. Both DI1 and DI2 input buffers have pull-down

resistors and can float if not in use. 6.0 Interrupts

6.0 Interrupts

The UT69R000 has 15 levels of internal interrupt prioritizing.

Upon the occurrence of an enabled non-masked interrupt, the

UT69R000 program flow (i.e., instruction counter) transfers to

the appropriate interrupt vector. The interrupt vector points to

an interrupt service routine. After completing the interrupt

service routine the program flow is returned to the main

program location. Table 1 shows a list of UT69R000 interrupts.

6.1 Interrupt Control

The Pending Interrupt Register, Mask Register, Status

Register, and Fault Register control and report interrupt

processing. These registers contain the following interrupt

information:

- Interrupt events (PI)

- Interrupt status, masked versus unmasked (MK)

- Interrupt status, enabled versus disabled

(STATUS bit 9)

- Machine error interrupts (FT)

26

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