OSCIN
CK1
CK2
CK3
CK4
STATE1
RA(19:0)
RD(15:0)
EXECUTE FETCH EXECUTE
OTR RA,SW
XXXX (hex)
OTR RA, SW
OD(7:0)
OD(7:0) Valid
Figure 23. Output Discrete Bus Timing
The UT69R000 requests control of the Operand buses at the
beginning of time period CK2 by asserting BRQ. On every
subsequent falling edge of OSCIN, the UT69R000 samples the
BGNT and BUSY inputs. When the UT69R000 detects on the
falling edge of OSCIN that BGNT has gone low and BUSY
has gone high, the UT69R000 is the new bus master and can
now control the Operand buses. The UT69R000 locks out any
other bus master from controlling the Operand buses by
asserting BGACK at the beginning of time period CK3 and
holding BGACK active until it is ready to relinquish control
of the Operand buses. The UT69R000 holds the BGACK
signal active until the beginning of the CK3 time period of the
next bus cycle when the UT69R000 no longer controls the
Operand buses.
5.0 Discrete Input/Output
To control external hardware and receive external information,
the UT69R000 has an 8-bit output discrete bus and two discrete
inputs. The discrete input function allows for easy gathering of
information from the subsystem. The output discrete bus
allows the UT69R000 to control subsystems via a combination
of hardware and software.
5.1 Output Discrete Bus
The UT69R000 has eight user-defined output discretes
(OD(7:0)). Output Register Instruction OTR Rd,SW governs
the logic state of each output discrete. The Status/Output
Discrete Register reflects the state of the output discretes.
Software can read the contents of this register by executing.
the Input Register Instruction INR Rd,SW.
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