59629855202VZC View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

59629855202VZC

RadHard MicroController

Aeroflex UTMC 

OSCIN

CK1

CK2

CK3

CK4

STATE1

OE

WE

RISC

ADDRESS

ADDRESS VALID (ACC)

NEXT ADDRESS

RISC

DATA

STRI

INSTRUCTION

DATA VALID (RSn)

NEXT

INSTRUCTION

Figure 18. STRI Instruction Typical Timing

Four signals make up the arbitration control bus -- Bus Request

(BRQ), Bus Grant (BGNT), Bus Busy ( BUSY), and Bus Grant

Acknowledge (BGACK) .

4.1 Operand Bus Cycle Operation

The timing diagrams in figures 20, 21, and 22 show signal

relationships for the UT69R000 during an operand bus cycle

operation. The UT69R000 performs one of four operations

involving bus cycles on the Operand buses: (1) Memory Read,

(2) Memory Write, (3) I/O Read, and (4) I/O Write. The

UT69R000 performs all four bus cycle operations similarly.

The M/IO and R/WR signals determine the precise type of bus

cycle operation. For the following discussion, refer to figures

20, 21, and 22.

When the Operand bus arbitration process is complete and the

UT69R000 controls the Operand address and data buses, time

period CK3 begins. The UT69R000 signal controls the

Operand port at the beginning of time period CK3 by asserting

BGACK. STATE1 transitions from low to high. At the same

time, the following signals become valid: R/WR, M/IO, and

the Operand Address bus RA(15:0). Control signals R/WR and

M/IO determine the direction and type of bus cycle

taking place.

One-half clock cycle after the beginning of time period CK4

or one full clock cycle after the start of time period CK3, DS

goes active low. After DS has asserted, the UT69R000 samples

the DTACK input on every subsequent rising edge of OSCIN

to determine the duration of CK4. A bus cycle terminates one-

half clock cycle after the rising edge of OSCIN when the

UT69R000 detects assertion of DTACK. At this time, the

Operand Address Bus A (15:0) and the Operand bus control

signals (R/WR, M/IO) select the memory or I/O location from

which the Operand Data is read, or to which the Operand Data

is written. The UT69R000 also samples the MPROT and

BTERR inputs on the same rising edge of OSCIN. These two

inputs indicate an error condition and terminate the current

bus cycle.

20

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