59629855202VZC View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

59629855202VZC

RadHard MicroController

Aeroflex UTMC 

OSCIN

CK1

CK2

CK3

CK4

STATE1

EXECUTE

FETCH

RA(19:0)

Immediate Address Fetch Address Valid Fetch Address Valid

RD(15:0)

Immediate Data

Fetch Instruction

Fetch Instruction

STATUS

(M/IO, R/WR)

DS

Control Valid

A(15:0)

Address Valid

D(15:0)

Note:

1. Examples of three clock cycle instructions include (long immediate accesses):

MOV Rd, FFFF (hex)

ADD Rd, FFFF (hex)

Data Read

Figure 17. Machine Cycle 3 (4 Clock Cycle Instructions)

Executing the LRI instruction begins when the falling edge of

OSCIN signals the start of time period CK1. At the beginning

of CK1, the data previously stored in the ACC becomes a valid

address on the instruction port address bus (RA(19:0)) and

STATE1 output becomes active indicating the UT69R000 is

executing an instruction.

The data on the data bus is read into the UT69R000 during time

period CK2. The function of the remainder of the bus cycle

(time periods CK3 and CK4) is the same as for other

instructions. STATE1 is high, indicating the next instruction

is being fetched from memory and is ready for execution during

the next bus cycle.

4.0 Operand Port

The UT69R000 Operand Data bus interface supports multiple

processor and direct memory access (DMA) configurations.

The Operand Address bus A(15:0), data bus D(15:0), and

memory control bus signals (DS, R/WR, and M/IO) are TTL-

compatible outputs that may be placed in a high-impedance

state. These signals are only active during bus cycles when the

UT69R000 is the current bus master. On other bus cycles, these

signals enter a high-impedance state so an alternate bus master

can control the port.

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