5962G9855202QXC View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

5962G9855202QXC

RadHard MicroController

Aeroflex UTMC 

OSCIN

CK1

CK2

CK3

CK4

STATE1

EXECUTE

FETCH

RA(19:0)

Fetch Address Valid Fetch Address Valid

RD(15:0)

Fetch Instruction

Fetch Instruction

STATUS

(M/IO, R/WR)

DS

Control Valid

A(15:0)

Address Valid

D(15:0)

Data Read

Note:

1. Examples of three clock cycle instructions include (operand port accesses):

LR Rd, Rs

STR Rd, Rs

Figure 16. Machine Cycle 2 (3 Clock Cycle Instructions)

3.1.2 LRI Instruction Bus Cycle

During an LRI instruction, the UT69R000 moves the

instruction data from the instruction memory to the

UT69R000.Figure 19 shows the timing diagram of the signal

relationships for the UT69R000 during an LRI Instruction Bus

Cycle.

Just as with the STRI instruction, before the UT69R000

executes the LRI instruction the system programmer must load

the UT69R000’s accumulator with the address from which the

data will be read. After the ACC is loaded with the address

information, LRI instruction execution can take place.

18

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