59629855201QXX View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

59629855201QXX

RadHard MicroController

Aeroflex UTMC 

OSCIN

CK1

CK2

CK3

CK4

STATE1

EXECUTE FETCH

RA(19:0)

Valid Address

Valid Address

Valid Address

RD(15:0)

Instruction Data

Note:

1. Examples of two clock cycle instructions include (internal operations):

MOV Rd, Rs

ADD Rd, Rs

Instruction Data

Instruction Data

Figure 15. Machine Cycle 1 (2 Clock Cycle Instructions)

If the instruction being executed requires access to the operand

bus, DS goes active. The UT69R000 samples the Data Transfer

Acknowledge (DTACK) on the next and every subsequent

rising edge of the processor clock. If DTACK is not low, the

UT69R000 extends time period CK4 until DTACK becomes

active or until an error condition is detected -- either Bus Error

(BTERR) or Memory Protect (MPROT) becomes active.

STATE1 remains high during the entire CK4 time period.

Figures 15, 16, and 17 show the timing relationships for CK1,

CK2, CK3, and CK4 during 2, 3, and 4 clock cycle instructions.

3.1 Instruction Port Operations

Most applications dedicate the instruction port to program

information. For these applications WE is always negated. The

UT69R000 can manipulate the instruction port through

instructions Store Register to Instruction Memory (STRI, write

access) and Load Register from Instruction Memory (LRI, read

access). Section 3.1.1 and 3.1.2 review the STRI and LRI

instructions.

17

3.1.1 STRI Instruction Bus Cycle

During an STRI instruction, instruction data moves from the

UT69R000 to the instruction memory. Figure 18 shows the

timing diagram of the signal relationships for the UT69R000

during STRI Instruction Bus Cycle Operation. Before the

UT69R00 executes the STRI instruction, the system

programmer must load the Accumulator Register with the

address which will receive the data. When the ACC is loaded

with the address information, the UT69R000 can begin

executing the STRI instruction.

Executing the STRI instruction begins when the falling edge

of OSCIN signals the start of time period CK1. At the beginning

of CK1, the data previously stored in the ACC becomes a valid

address on the instruction port address bus (RA(19:0)) and

STATE1 output becomes active, indicating the UT69R000 is

executing an instruction.

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