5962G9855201QZX View Datasheet(PDF) - Aeroflex UTMC
Part Name
Description
Manufacturer
5962G9855201QZX Datasheet PDF : 62 Pages
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Pending Interrupt Register
The Pending Interrupt Register (PI) contains information on
pending interrupts attempting to vector the Instruction Counter
Register to a new location. Software or hardware controls the
Pending Interrupt Register contents. Any system interrupt,
when active, sets the corresponding bit in the register. OTR
and INR instruction can also set, clear, and read the Pending
Interrupt Register (figure 11).
Instruction INR Rd, PI stores the PI contents in the destination
register. OTR Rd, PI loads the PI with the contents of the
destination register. OTR Rd, RPI clears the PI register. For
each bit set, to a logic one, in the destination register the
corresponding PI bit is cleared. To clear the PI, first read the
PI, then clear only the bits set to a logic one. Reading, then
clearing the PI prevents the inadvertent clearing of interrupts
occurring during execution of an OTR Rd, RPI command.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P M I UFUU T I T I I I I I N
W C NS I S S I N I NNNNN /
D H T R P RR M TM T T T T TU
N EO3O21 A1B 2 364 7
MSB
LSB
Figure 11. The Pending Interrupt Register (PI)
Example:
CLEAR: INR Rd, PI
OTR Rd, RPI
To generate a software interrupt clear the corresponding bit in
the PI register before writing to the PI register.
Example:
WRITE:
MOV R1, 1000 (hex)
OTR R1, RPI
OTR R1, PI
Note: Do not enable interrupts while the PI is non-zero.
Bit Number
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Mnemonic
PWDN
MCHE
INT0
USR3
FIPO
USR2
USR1
TIMA
INT1
TIMB
INT2
Description
Power Fail
Machine Error Interrupt
External Interrupt 0
Software Interrupt 3
Fix Point Overflow
Software Interrupt 2
Software Interrupt 1
Timer A Interrupt
External Interrupt 1
Timer B Interrupt
External Interrupt 2
10
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