UT1750AR(2003) View Datasheet(PDF) - Aeroflex UTMC
Part Name
Description
Manufacturer
UT1750AR Datasheet PDF : 55 Pages
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OPERAND DATA BUS CONTROL
Continued from page 5.
PIN NAME
AS
PIN NUMBER
FLTPK PGA
115
C3
TYPE
TTO
ACTIVE
AL
DESCRIPTION
Address Strobe. Indicates a valid address on the Operand
Address bus. UT1750AR places AS in a high-impedance
state when it does not control the Operand busses.
DS
116
B2 TTO
AL
Data Strobe. Indicates valid data is on the Operand Data bus.
The UT1750AR places DS in a high-impedance state when
it does not control the Operand busses.
RISC MEMORY CONTROL
PIN NAME
OE
WE
PIN NUMBER
FLTPK PGA
42
R12
43
R13
TYPE
TTO
TTO
ACTIVE
AL
AL
DESCRIPTION
Output Enable RISC Memory. This signal
allows RISC memory to place data on the RISC instruction
data bus. The Store Register to Instruction Memory (STRI)
instruction removes OE during the CK2 internal clock
cycle. OE enters a high-impedance state when the
UT1750AR is in the test mode (TEST = 0).
Write Enable RISC Memory. This signal allows the
UT1750AR to write to RISC instruction memory. The
Store Register to Instruction Memory (STRI) instruction
asserts WE during the CK2 internal clock cycle. WE
enters a high-impedance state when the UT1750AR is in
the test mode (TEST = 0).
UART CONTROL/TIMER CLOCK
PIN NAME
UARTIN
PIN NUMBER
FLTPK PGA
127
F1
TYPE
TUI
ACTIVE
AH
DESCRIPTION
UART Input. The UT1750AR receives serial data
through this input. The serial data is stored in the
UT1750AR’s Receiver Buffer Register (RCVR). It is tied
to an internal pull-up resistor.
UARTOUT 128
G1 TTO
AH
UART Output. The serial data stored in the UT1750AR’s
Transmitter Buffer Register (TXMT) is transmitted
through this output. The UART output is fixed at 9600
baud, with eight data bits, odd-parity, and one stop bit.
UARTOUT enters a high-impedance state when the
UT1750AR is in the test mode (TEST=0). (9600 baud @
TIMCLK = 12MHz)
Continued on page 7.
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