UT1750AR(2003) View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

UT1750AR
(Rev.:2003)

RadHard RISC Microprocessor

Aeroflex UTMC 

OPERAND DATA BUS ARBITRATION

PIN NAME

BRQ

BGNT

BUSY

BGACK

PIN NUMBER

FLTPK PGA

118

D2

TYPE

TTO

ACTIVE

AL

DESCRIPTION

Bus Request. The UT1750AR asserts this signal to indicate

it is requesting control of the Operand data bus (D0 - D15).

BRQ enters a high-impedance state when the UT1750AR is

in the test mode (TEST = 0).

119

E3

TUI

AL

Bus Grant. When asserted, this signal indicates the

UT1750AR may take control of the Operand data bus. It is

tied to an internal pull-up resistor.

120

C1 TUI

AL

Bus Busy. A bus master asserts this input to inform the

UT1750AR that another bus master is using the Operand

data bus. It is tied to an internal pull-up resistor.

117

B1 TTO

AL

Bus Grant Acknowledge Output. The UT1750AR asserts

this signal to indicate it is the current bus master. When low,

BGACK inhibits other devices from becoming the bus

master. When the UT1750AR relinquishes control of the

bus, BGACK enters a high-impedance state.

OPERAND DATA BUS CONTROL

PIN NAME

OP/IN

DTACK

PIN NUMBER

FLTPK PGA

113

A2

121

E2

TYPE

TTO

TUI

ACTIVE

--

AL

DESCRIPTION

Operand/Instruction. This indicates whether the

UT1750AR’s current bus cycle is for Data (high) or

Instruction (low) acquisition. OP/IN remains in a high

state whenever a bus cycle (Memory or I/O) is not an

instruction fetch.

Data Transfer Acknowledge. This signal tells the

UT1750AR that a data transfer has been acknowledged

and the UT1750AR can complete the bus cycle. To assure

the UT1750AR operates with no wait states,DTACK can

be tied low. DTACK is tied to an internal pull-up resistor.

M/IO

R/WR

112

B3 TTO

114

C4 TTO

--

Memory or I/O. Indicates whether the current bus cycle

is for memory (high) or I/O (low). It remains in the high-

impedance state during bus cycles when the UT1750AR

does not control the Operand busses.

--

Read/Write. Indicates the direction of data flow with

respect to the UT1750AR. R/WR high means the

UT1750AR is attempting to read data from an external

device, and R/WR low means the UT1750AR is

attempting to write data to an external device. R/WR

remains in a high-impedance state when the UT1750AR

does not control the Operand busses.

Continued on page 6.

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