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M-982-02S View Datasheet(PDF) - Clare Inc => IXYS

Part Name
Description
Manufacturer
M-982-02S
Clare
Clare Inc => IXYS Clare
M-982-02S Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
M-982-02
Specifications (continued)
Parameter
Conditions
Clock
Tri-state
Operation
SIGIN pin
Voltage range
Input impedance
Input spectrum
External clock
VIL
connected to XIN pin
VIH
Duty cycle
XIN, XOUT with crystal Capacitance
osc. active
Internal resistance
Power up (TPU)
X358 pin
VOL
VOH
tEN,(High Z to Low Z)
tDE,(Low Z to High )Z
Duty cycle
CL = 50 pF,
RL = 100 kW
-
f=500 Hz
-
XOUT open
XOUT open
XOUT open
-
-
PD hi to lo
CL = 20 pF,
ISINK = -1mA
CL = 20 pF,
ISOURCE =1mA
CL = 20 pF
-
-
Unless otherwise noted, VDD - VSS = 5V, Ta = 25°C, PD at logical low state, and XRANGE at a logical high state.
Power levels are in dBm referenced to 600 ohm.
Notes:
DC voltages are referenced to VSS.
1. Per tone.
Min
-6.5
80
-
-
VDD-0.2
40
-
20
-
-
VDD - 0.2
40
250
250
Max
Units Notes
VDD
V
-
k
28
kHz
0.2
V
-
V
60
%
10
pF
-
MW
30
ms
0.2
V
-
V
60
%
ns
ns
Pin Functions
Pin
DET 1
DET 2
DET 3
DET 4
DET 5
EN
OE
SIGIN
STROBE
VDD
VREF
VSS
X358
XIN
XOUT
XRANGE
MODE
PD
Funtion
Active high tri-state output, detect for 350 Hz.
Active high tir-state ooutput, detect for 400/620 Hz.
(See Note.)
Active high tri-state output, detect for 440 Hz.
Active high tri-state output, detect for 480 Hz.
Active high tri-state output, detect for 425 Hz.
Active high enabled, when low drives STROBE low.
Active high input. When low tri-state DET n pins.
Analog signal input (internally capacitive coupled).
Active high output, indicates valid DET n.
Most positive power supply input pin.
Internally generated mid-power supply voltage
(output).
Most negative power supply input pin.
Buffered oscillator output (3.58 MHz).
Crystal oscillator or digital clock input.
Crystal oscillator output. Used only with a crystal.
Use X358 when clock output signal is required.
Active low input. Adds 10 dB of gain to input stage.
Compatibility selection. Connection to VSS selects
400 Hz detection. (M-981-02 emulation.) Connection
to VDD or no connection selects 620 Hz detection.
Power-down operation, logic high inhibits internal
clock. Internal pulldown resistor.
Note: This output indicates 400 Hz detect when MODE is connected to VSS and 620
Hz detect when open, or connected to VDD.
Call Progress Tones
Frequency (HZ)
1
2
350
440
400
Off
440
Off
440
480
440
620
480
Off
480
620
350
Off
620
Off
941
1209
425
Off
Use
Dial Tone
Special
Alert Tone
Audible Ring
Pre-empt
Bell High Tone
Reorder (Bell Low)
Special
Special
* DTMF “ ”
European
Rev. 4
www.clare.com
3
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