MTV030N View Datasheet(PDF) - Myson Century Inc
Part Name
Description
Manufacturer
MTV030N Datasheet PDF : 21 Pages
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MYSON
TECHNOLOGY
MTV030
tents of CH4-CH0 is greater than or equal to 18, it will be regarded as equal to 17. See Table 2
and Table 3 for detail description of this operation.
b7 b6 b5 b4 b3 b2 b1 b0
Column 15 -
HORR
MSB
LSB
HORR - Specify the resolution of a horizontal display line, and the increment of each step is 12 dots. That is,
the pixels' number per H line equal to HORR*12. It is recommended that HORR should be greater
than or equal to 36 and smaller than 150M / (Hfreq*12). The initial value is 40 after power up.
b7 b6 b5 b4 b3 b2 b1 b0
Column 16 -
-
-
RSPACE
MSB
LSB
RSPACE - Define the row to row spacing in unit of horizontal line. That is, extra RSPACE horizontal lines will
be appended below each display row, and the maximum space is 31 lines. The initial value is 0
after power up.
b7
b6
b5
b4
b3
b2
b1
b0
Column 17 OSDEN BSEN SHADOW FBEN BLEND WENCLR RAMCLR FBKGC
OSDEN - Activate the OSD operation when this bit is set to "1". The initial value is 0 after power up.
BSEN - Enable the bordering and shadowing effect.
SHADOW - Bordering and shadowing effect select bit. Activate the shadowing effect if this bit is set, otherwise
the bordering is chosen.
FBEN - Enable the fade-in/fade-out and blending-in/blending-out effect when OSD is turned on from off state
or vice verca.
BLEND - Fade-in/fade-out and blending-in/blending-out effect select bit. Activate the blending-in/blending-out
function if this bit is set, otherwise the fade-in/fade-out function is chosen. These function roughly
takes about 0.5 second to fully display the whole menu or to disappear completely.
WENCLR - Clear all WEN bits of window control registers when this bit is set to "1". The initial value is 0 after
power up.
RAMCLR - Clear all ADDRESS bytes, BGR, BGG, BGB and BLINK bits of display registers when this bit is set
to "1". The initial value is 0 after power up.
FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs high during the
displaying of characters or windows, otherwise, it outputs high only during the displaying of charac-
ter.
B7
Column 18 TRIC
b6
FSS
b5
VMEN
b4
b3
SELVCL HSP
b2
b1
b0
VSP VCO1 VCO0
TRIC - Define the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That is,
while OSD is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins are
in high impedance state. The initial value is 0 after power up.
11/21
MTV030 Revision 1.0 10/15/1999
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