AD679BJ View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD679BJ

14-bit 128 kSPS complete sampling ADC

Analog Devices 

AD679

TIMING SPECIFICATIONS

(All device types TMIN to TMAX, VCC = +12 V ؎ 5%, VEE = –12 V ؎ 5%,

VDD = +5 V ؎ 10%)

Parameter

Symbol Min Max Units

SC Delay

tSC

Conversion Time

tC

Conversion Rate1

tCR

Convert Pulse Width tCP

Aperture Delay

tAD

Status Delay

tSD

Access Time2, 3

tBA

Float Delay5

tFD

Output Delay

tOD

Format Setup

tFS

OE Delay

tOE

Read Pulse Width

tRP

Conversion Delay

tCD

EOCEN Delay

tEO

50

ns

6.3 µs

7.8 µs

0.097 3.0 µs

5

20 ns

0

400 ns

10 100 ns

10

574 ns

10 80 ns

0

ns

100

ns

20

ns

195

ns

400

ns

50

ns

NOTES

1Includes Acquisition Time.

2Measured from the falling edge of OE/EOCEN (0.8 V) to the time at which the

data lines/EOC cross 2.0 V or 0.8 V. See Figure 4.

3COUT = 100 pF.

4COUT = 50 pF.

5Measured from the rising edge of OE/EOCEN (2.0 V) to the time at which the

output voltage changes by 0.5. See Figure 4; COUT = 10 pF.

Specifications subject to change without notice.

ORDERING GUIDE1

Model2 Package

Temperature

Range

Tested

and

Package

Specified Option3

AD679JN 28-Pin Plastic DIP

AD679KN 28-Pin Plastic DIP

AD679JD 28-Pin Ceramic DIP

AD679KD 28-Pin Ceramic DIP

AD679AD 28-Pin Ceramic DIP

AD679BD 28-Pin Ceramic DIP

AD679SD 28-Pin Ceramic DIP

AD679TD 28-Pin Ceramic DIP

AD679AJ 44-Lead Ceramic JLCC

AD679BJ 44-Lead Ceramic JLCC

AD679SJ 44-Lead Ceramic JLCC

AD679TJ 44-Lead Ceramic JLCC

0°C to +70°C

0°C to +70°C

0°C to +70°C

0°C to +70°C

–40°C to +85°C

–40°C to +85°C

–55°C to +125°C

–55°C to +125°C

–40°C to +85°C

–40°C to +85°C

–55°C to +125°C

–55°C to +125°C

AC

AC + DC

AC

AC + DC

AC

AC + DC

AC

AC + DC

AC

AC + DC

AC

AC + DC

N-28

N-28

D-28

D-28

D-28

D-28

D-28

D-28

J-44

J-44

J-44

J-44

NOTES

1For parallel read (14-bits) interface to 16-bit buses, see AD779.

2For details grade and package offerings screened in accordance with MIL-STD-

883, refer to the Analog Devices Miliary Products Databook or current AD679/

883B data sheet.

3N = Plastic DIP; D = Ceramic DIP; J = J-Leaded Ceramic Chip Carrier.

Figure 1. Conversion Timing

Figure 2. Output Timing

Figure 3. EOC Timing

Figure 4. Load Circuit for Bus Timing Specifications

–4–

REV. C

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