AD9742ARUZRL7 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9742ARUZRL7 Datasheet PDF : 32 Pages
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Data Sheet
Parameter
Multitone Power Ratio (8 Tones at 400 kHz Spacing)
fCLOCK = 78 MSPS; fOUT = 15.0 MHz to 18.2 MHz
0 dBFS Output
−6 dBFS Output
−12 dBFS Output
−18 dBFS Output
Min
Typ
Max
65
67
65
63
1 Measured single-ended into 50 Ω load.
2 Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
3 Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter
DIGITAL INPUTS1
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulse Width (tLPW)
CLK INPUTS2
Input Voltage Range
Common-Mode Voltage
Differential Voltage
Min
Typ
Max
2.1
3
0
0.9
−10
+10
−10
+10
5
2.0
1.5
1.5
0
3
0.75
1.5
2.25
0.5
1.5
1 Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.
2 Applicable to CLK+ and CLK− inputs when configured for differential or PECL clock input mode.
DB0–DB11
CLOCK
IOUTA
OR
IOUTB
tS
tPD
tH
tLPW
tST
0.1%
0.1%
Figure 2. Timing Diagram
AD9742
Unit
dBc
dBc
dBc
dBc
Unit
V
V
µA
µA
pF
ns
ns
ns
V
V
V
Rev. C | Page 5 of 32
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