Data Sheet
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 34 shows the AD9742 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly terminated
50 Ω cable since the nominal full-scale current, IOUTFS, of 20 mA
flows through the equivalent RLOAD of 25 Ω. In this case, RLOAD
represents the equivalent load resistance seen by IOUTA or
IOUTB. The unused output (IOUTA or IOUTB) can be connected
to ACOM directly or via a matching RLOAD. Different values of
IOUTFS and RLOAD can be selected as long as the positive compliance
range is adhered to. One additional consideration in this mode
is the integral nonlinearity (INL), discussed in the Analog Outputs
section. For optimum INL performance, the single-ended, buffered
voltage output configuration is suggested.
AD9742
IOUTFS = 20mA
IOUTA 22
50Ω
IOUTB 21
25Ω
VOUTA = 0V TO 0.5V
50Ω
Figure 34. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 35 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9742 output current. U1 maintains IOUTA (or IOUTB) at a
virtual ground, minimizing the nonlinear output impedance
effect on the DAC’s INL performance as described in the Analog
Outputs section. Although this single-ended configuration typically
provides the best dc linearity performance, its ac distortion
performance at higher DAC update rates may be limited by U1’s
slew rate capabilities. U1 provides a negative unipolar output
voltage, and its full-scale output voltage is simply the product of
RFB and IOUTFS. The full-scale output should be set within U1’s
voltage output swing capabilities by scaling IOUTFS and/or RFB. An
improvement in ac distortion performance may result with a
reduced IOUTFS since U1 will be required to sink less signal current.
COPT
AD9742
IOUTA 22
IOUTFS = 10mA
IOUTB 21
200Ω
RFB
200Ω
U1
VOUT = IOUTFS × RFB
Figure 35. Unipolar Buffered Voltage Output
AD9742
POWER AND GROUNDING CONSIDERATIONS,
POWER SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these application circuits,
the implementation and construction of the printed circuit
board is as important as the circuit design. Proper RF techniques
must be used for device selection, placement, and routing as
well as power supply bypassing and grounding to ensure
optimum performance. Figure 40 to Figure 43 illustrate the
recommended printed circuit board ground, power, and signal
plane layouts implemented on the AD9742 evaluation board.
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies
is common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise will occur over the spectrum from tens of
kHz to several MHz. The PSRR versus frequency of the AD9742
AVDD supply over this frequency range is shown in Figure 36.
85
80
75
70
65
60
55
50
45
40
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 36. Power Supply Rejection Ratio (PSRR)
Note that the ratio in Figure 36 is calculated as amps out/volts
in. Noise on the analog power supply has the effect of modulating
the internal switches, and therefore the output current. The
voltage noise on AVDD, therefore, will be added in a nonlinear
manner to the desired IOUT. Due to the relative different size of
these switches, the PSRR is very code dependent. This can produce
a mixing effect that can modulate low frequency power supply
noise to higher frequencies. Worst-case PSRR for either one of
the differential DAC outputs will occur when the full-scale current
is directed toward that output. As a result, the PSRR measurement
in Figure 36 represents a worst-case condition in which the
digital inputs remain static and the full-scale output current of
20 mA is directed to the DAC output being measured.
Rev. C | Page 17 of 32