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ADF4106BCP View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADF4106BCP
ADI
Analog Devices ADI
ADF4106BCP Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADF4106
3.5
VDD = 3V
3.0 VP = 3V
2.5
2.0
1.5
1.0
0.5
0
50
100
150
200
250
300
PRESCALER OUTPUT FREQUENCY
TPC 13. DIDD vs. Prescaler Output Frequency
6
4
VP = 5V
ICP = 5mA
2
0
2
4
6
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VCP V
TPC 14. Charge Pump Output Characteristics
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The Reference Input stage is shown in Figure 2. SW1 and SW2
are normally-closed switches. SW3 is normally-open. When
Powerdown is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
POWER-DOWN
CONTROL
REFIN
NC 100k
SW2
NC
SW1
BUFFER
TO R COUNTER
NO SW3
NC = NO CONNECT
Figure 2. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 3. It is followed by a 2-stage
limiting amplifier to generate the CML clock levels needed for the
prescaler.
BIAS
GENERATOR
1.6V
AVDD
500
500
RF A
IN
RF B
IN
PRESCALER (P/P + 1)
The dual modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A and B
counters. The prescaler is programmable. It can be set in soft-
ware to 8/9, 16/17, 32/33 or 64/65. It is based on a synchronous
4/5 core. There is a minimum divide ratio possible for fully
contiguous output frequencies. This minimum is determined by
P, the prescaler value and is given by: (P2 P).
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feed-
back counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dual modulus
prescaler make it possible to generate output frequencies which
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
fVCO
P
B
A
fREFIN
fVCO
= [(P × B) + A] ×
fREFIN
R
Output Frequency of external voltage controlled
oscillator (VCO).
Preset modulus of dual modulus prescaler
(8/9, 16/17, etc.,).
Preset Divide Ratio of binary 13-bit counter
(3 to 8191).
Preset Divide Ratio of binary 6-bit swallow
counter (0 to 63).
External reference frequency oscillator.
AGND
Figure 3. RF Input Stage
–8–
REV. 0
 

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