DATA SHEET
MAS 35x9F
Table 3–16: Codec control registers on I2C subaddress 6Chex, continued
Register
Address
(hex)
Function
Name
INPUT MODE SELECT
00 08
Input Mode Setting
bit[15]
Mono switch
0
stereo input mode
1
left channel is copied into the right channel
bit[14:2] Reserved, must be set to 0
bit[1:0]
Deemphasis select
0
deemphasis off
1
deemphasis 50 µs
2
deemphasis 75 µs
ADC_IN_MODE
OUTPUT MODE SELECT
00 06
00 07
D/A Converter Source Mixer
MIX ADC scale
MIX DSP scale
bit[15:8]
Linear scaling factor (hex)
0
off
20
50 % (−6 dB gain)
40
100 % (0 dB gain)
7f
200 % (+6 dB gain)
In the sum of both mixing inputs exceeds 100 %, clipping may occur in the
successive audio processing.
DAC_IN_ADC
DAC_IN_DSP
00 0E
D/A Converter Output Mode
bit[15]
Mono switch
0
stereo through
1
mono matrix applied
bit[14]
Invert right channel
0
through
1
right channel is inverted
bit[1:0]
Reserved, must be set to 0
In order to achieve more output power a single loudspeaker can be connected
as a bridge between pins OUTL and OUTR. In this mode bit[15] and bit[14]
must be set.
DAC_OUT_MODE
Micronas
June 30, 2004; 6251-505-1DS
47