DATA SHEET
MAS 35x9F
Table 3–2: I2C subaddresses
Sub-
address
(hex)
I2C-
Register
Name
Function
Direct Configuration
6A
CONTROL Controller writes to
MAS 35x9F CONTROL
register
76
DCCF
Controller writes to first
DC/DC configuration reg-
ister
77
DCFR
Controller writes to
second DC/DC configura-
tion register
DSP Core Access
68
data_write Controller writes to
MAS 35x9F DSP
69
data_read Controller reads from
MAS 35x9F DSP
Codec Access
6C
codec_write Controller writes to
MAS 35x9F codec regis-
ter
6D
codec_read Controller reads from
MAS 35x9F codec regis-
ter
3.2.1. Write Direct Configuration Registers
S DW W A subaddr. A d3,d2 A d1,d0 A P
The write protocol for the direct configuration registers
only consists of device address, subaddress and one
16-bit data word.
3.2.2. Read Direct Configuration Register
S DW W A subaddr. A S DR W A
d3,d2 A d1,d0 N P
To check the PUP1 and PUP2 power-up flags, it is
necessary to read back the content of the direct config-
uration registers.
Example: I2C write access
S
DW
WA
Example: I2C read access
S
DW
WA
subaddress
subaddress
A high byte data A low byte data W A P
AS
DR
WA
high byte data A low byte data W N P
SDA
1
W = Wait
S
SCL
0
A = Acknowledge (Ack)
P
N = Not Acknowledge (NAK)
S = Start
P = Stop
Fig. 3–1: Example of an I2C bus protocol for the MAS 35x9F (MSB first; data must be stable while clock is high)
Micronas
June 30, 2004; 6251-505-1DS
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