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STA015T View Datasheet(PDF) - STMicroelectronics

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Description
Manufacturer
STA015T Datasheet PDF : 44 Pages
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STA015-STA015B-STA015T
Figure 8. Serial Input Interface Clocks
SDI
DATA IGNORED
SCKR
SCLK_POL=0
SCKR
SCLK_POL=4
BIT_EN
DATA VALID
D98AU968A
DATA IGNORED
3. INTERFACE DESCRIPTION
3.1 - Serial Input Interface
STA015 receives the input data (MSB first)
through the Serial Input Interface (Fig.7). It is a
serial communication interface connected to the
SDI (Serial Data Input) and SCKR (Receiver Se-
rial Clock).
The interface can be configured to receive data
sampled on both rising and falling edge of the
SCKR clock. The BIT_EN pin, when set to low,
forces the bitstream input interface to ignore the
incoming data. For proper operation BIT_EN line
should be toggled only when SCKR is stable low
(for both SCLK_POL configuration). The possible
configurations are described in Fig. 8.
3.2 - GPSO Output Interface
In order to retrieve ADPCM encoded data a Gen-
eral Purpose Serial Output interface is available
(in TQFP44 and LFBGA64 packages only). The
maximum frequency for GPSO_SCKR clock is
Figure 9. PCM Output Formats
the DSP system clock frequency divided by 3
(i.e. 8.192 MHz @ 24.58MHz). The interface is
based on a simple and configurable 3-lines proto-
col, as described by figure 10.
3.3 - PCM Output Interface
The decoded audio data are output in serial PCM
format. The interface consists of the following sig-
nals:
SDO
PCM Serial Data Output
SCKT
PCM Serial Clock Output
LRCLK Left/Right Channel Selection Clock
The output samples precision is selectable from
16 to 24 bits/word, by setting the output precision
with PCMCONF (16, 18, 20 and 24 bits mode)
register. Data can be output either with the most
significant bit first (MS) or least significant bit first
(LS), selected by writing into a flag of the
PCMCONF register.
Figure 9 gives a description of the several
STA015 PCM Output Formats. The sample rates
set decoded by STA015 is described in Table 1.
LRCKT
SDO
SDO
16 SCLK Cycles
16 SCLK Cycles
16 SCLK Cycles
16 SCLK Cycles
16 SCLK Cycles
M
LM
LM
LM
L PCM_ORD = 0
S
SS
SS
SS
S PCM_PREC is 16 bit mode
L
ML
ML
ML
M PCM_ORD = 1
S
SS
SS
SS
S PCM_PREC is 16 bit mode
LRCKT
SDO
SDO
SDO
SDO
32 SCLK Cycles
32 SCLK Cycles
32 SCLK Cycles
32 SCLK Cycles
32 SCLK Cycles
M
S
L0
M
S
S
L
0
M
S
S
L0
S
M
S
L0
S
PCM_FORMAT = 1
PCM_DIFF = 1
0M
S
L
S
0
M
S
L
S
0M
S
L
0
M
S
S
L PCM_FORMAT = 0
S PCM_DIFF = 0
0M
S
L 0 0M
S
S
L
S
0
0
M
S
L
S
0
0M
S
L
S
0
PCM_FORMAT = 0
PCM_DIFF = 1
MSB M
S
L
S
MSB
M
S
L
S
MSB
M
S
L
S
MSB
M
S
L PCM_FORMAT = 1
S PCM_DIFF = 1
Table 1: MPEG Sampling Rates (KHz)
MPEG 1
48
44.1
32
MPEG 2
24
22.05
16
MPEG 2.5
12
11.025
8
10/44
 

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