STA014-STA014B-STA014T
In this mode the fractional part of the PLL is dis-
abled and the audio clocks are generated at
nominal rates. Fig. 6 describes the default
DATA_REQ signal behaviour. Programming
STA014 it is possible to invert the polarity of the
DATA_REQ line (register REQ_POL).
Figure 6. DATA_REQ control line
SOURCE STOPS TRANSMITTING DATA
SOURCE STOPS TRANSMITTING DATA
DATA_REQ
SOURCE SEND DATA TO STA015
D00AU1144
figuration registers of the device. The DAC con-
nected to STA014 can be initialized during this
mode (set MUTE to 1).
PLAY
X
X
MUTE
0
1
Clock State PCM Output
Not Running
0
Running
0
Init Mode
"PLAY" and "MUTE" changes are ignored in this
mode. The internal state of the decoder will be
updated only when the decoder changes from the
state "init" to the state "decode". The "init" phase
ends when the first decoded samples are at the
output stage of the device.
2.4 - STA014 Decoding States
There are three different decoder states: Idle,
Init, and Decode. Commands to change the de-
coding states are described in the STA014 I2C
registers description.
Idle Mode
In this mode (entered after a S/W or H/W reset)
the decoder is waiting for the RUN command.
This mode should be used to initialize the con-
Figure 7. MPEG Decoder Interfaces.
Decode Mode
This mode is completely described by the follow-
ing table:
PLAY
0
0
1
1
MUTE
0
1
0
1
Clock State
PCM
Output
Decoding
Not Running 0
No
Running
0
No
Running Decoded Yes
Samples
Running
0
Yes
DATA
SOURCE
DATA_REQ
SDI
SCKR
BIT_EN
µP
XTI XTO FILT
IIC
SCL
SDA
PLL
IIC
MPEG
DECODER
SERIAL AUDIO INTERFACE
RX
TX
SDO
SCKT
LRCKT
DAC
D98AU912
OCLK
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