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PKD01EP View Datasheet(PDF) - Analog Devices

Part Name
Description
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PKD01EP Datasheet PDF : 18 Pages
First Prev 11 12 13 14 15 16 17 18
THEORY OF OPERATION
The typical peak detector uses voltage amplifiers and a diode or
an emitter follower to charge the hold capacitor, CH, indirect-
ionally (see Figure 1). The output impedance of A plus D1’s
dynamic impedance, rd, make up the resistance which deter-
mines the feedback loop pole. The dynamic impedance is
rd
=
kT
qId
,
where
Id
is
the
capacitor
charging
current.
The pole moves toward the origin of the S plane as Id goes to
zero. The pole movement in itself will not significantly lengthen
the acquisition time since the pole is enclosed in the system
feedback loop.
VIN
INPUT
VOUT (A) = V IN (A) ؋ AV (A)
A
VOUT
+
ROUT
D1
VH
C
rd
CH
OUTPUT
Figure 1. Conventional Voltage Amplifier Peak Detector
When the moving pole is considered with the typical frequency
compensation of voltage amplifiers however, there is a loop stability
problem. The necessary compensation can increase the required
acquisition time. ADI’s approach replaces the input voltage ampli-
fier with a transconductance amplifier (see Figure 2).
The PKD01 transfer function can be reduced to:
VOUT =
1
1
VIN 1 + sCH + 1
1 + sCH
gm gm ROUT
gm
where: gm Ϸ 1 µA/mV, ROUT Ϸ 20 M.
The diode in series with A’s output (see Figure 2) has no effect
because it is a resistance in series with a current source. In
addition to simplifying the system compensation, the input
transconductance amplifier output current is switched by cur-
rent steering. The steered output is clamped to reduce and match
any charge injection.
VIN
INPUT
IOUT (A) = V IN (A) ؋ gm (A)
A
IOUT
D1 VH
ROUT
CH
C
OUTPUT
VOUT
Figure 2. Transconductance Amplifier Peak Detector
Figure 3 shows a simplified schematic of the reset gm amplifier,
B. In the track mode, Q1 and Q4 are ON and Q2 and Q3 are
OFF. A current of 2I passes through D1, I is summed at B and
passes through Q1, and is summed with gmVIN. The current sink
can absorb only 3I, thus the current passing through D2 can
PKD01
only be: 2K – gm VIN. The net current into the hold capacitor
node then, is gmVIN [IH = 2I – (2I – gmVIN)]. In the hold mode,
Q2 and Q3 are ON while Q1 and Q4 are OFF. The net current
into the top of D1 is –I until D3 turns ON. With Q1 OFF, the
bottom of D2 is pulled up with a current I until D4 turns ON,
thus, D1 and D2 are reverse biased by <0.6 V, and charge injec-
tion is independent of input level.
The monolithic layout results in points A and B having equal
nodal capacitance. In addition, matched diodes D1 and D2 have
equal diffusion capacitance. When the transconductance ampli-
fier outputs are switched open, points A and B are ramped
equally, but in opposite phase. Diode clamps D3 and D4 cause
the swings to have equal amplitudes. The net charge injection
(voltage change) at node C is therefore zero.
V+
I
2I
A
D1
C
D2
B
D3
C
D4
CH
6
Q1 Q2
Q3 Q4
A
LOGIC
VIN
gm V IN
B CONTROL
3I
3I
A > B = PEAK DETECT
VA < B = PEAK HOLD
Figure 3. Transconductance Amplifier with Low Glitch
Current Switch
The peak transconductance amplifier, A is shown in Figure 4.
Unidirectional hold capacitor charging requires diode D1 to be
connected in series with the output. Upon entering the peak
hold mode D1 is reverse-biased. The voltage clamp limits charge
injection to approximately 1 pC and the hold step to 0.6 mV.
Minimizing acquisition time dictates a small CH capacitance. A
1000 pF value was selected. Droop rate was also minimized by
providing the output buffer with an FET input stage. A cur-
rent cancellation circuit further reduces droop current and
minimizes the gate current’s tendency to double for every 10°
temperature change.
V+
I
2I
D3
D1
D2
rd
D4
C
CH
6
Q1 Q2
Q3 Q4
A
LOGIC
VIN
gm V IN
B CONTROL
3I
3I
A > B = PEAK DETECT
VA < B = PEAK HOLD
Figure 4. Peak Detecting Transconductance Amplifier
with Switched Output
REV. A
–11–
 

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