AccessRunner ADSL-USB Modem Device Set Data Sheet
BCLKIO (GPIO38) 30
I2C_SCL (GPIO16) 11
I2C_SDA (GPIO15) 12
Table 3-1. P5200 UIC Hardware Signal Definitions (Continued)
CX11627 ADDP SERIAL CHANNEL INTERFACE
Receive ATM0 Start of Cell. Connect to ADDP RXSOC0.
Receive AS0/ATM0 Data Clock. Connect to ADDP R_CLK_LS0.
Receive AS0/ATM0 Serial Data. Connect to ADDP R_DAT_LS0.
Transmit ATM0 Start of Cell. Connect to ADDP TXSOC0.
Transmit LS0/ATM0 Data Clock. Connect to ADDP T_CLK_LS0.
Transmit LS0/ATM0 Serial Data. Connect to ADDP T_DAT_LS0.
CX20431 AFE AND CX20441 LD CONTROL
AFE Reset. Active low reset output to the AFE and the LD. Connect
to AFE POR# and to LD PWRDWN#.
Line Driver Power Control. Optionally, connect to LD PWRDWN#
when it is desired to power down only the LD.
Off-Hook Detect. Active low; indicates POTS off-hook event. Used
for G.lite Mode only. Connect to off-hook detector circuit.
Inner/Outer Pair Select. Connect to wire-pair selection circuit.
Receive Pad. Connect to receive pad circuitry in hybrid.
SERIAL EEPROM INTERFACE
Serial EEROM Clock. Connect to EEPROM clock input.
Serial EEROM Data. Connect to EEPROM data line.
JTAG Reset. A high-to-low transition on this signal forces the TAP
controller into a logic reset state. This pin has an internal pullup, and it
conforms to IEEE 1149.1 JTAG specification.
JTAG Test Clock. This is the boundary scan clock input signal. This
pin has an internal pullup, and it conforms to IEEE 1149.1 JTAG
JTAG Test Mode Select. This signal controls the operation of the
TAP controller. This pin has an internal pull-up, and it conforms to
IEEE 1149.1 JTAG specification.
JTAG Test Input. This signal contains serial data that is shifted in on
the rising edge of TCK. The pin has an internal pullup, and it conforms
to IEEE 1149.1 JTAG specification.
JTAG Test Output Data. This is the three-stateable boundary scan
data output signal from the MCU, and it is shifted out on the falling
edge of TCK. It conforms to IEEE 1149.1 JTAG specification.