ADSP-2185NBSTZ-320 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-2185NBSTZ-320 Datasheet PDF : 48 Pages
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ADSP-218xN
ESD DIODE PROTECTION
During the power-up sequence of the DSP, differences in the
ramp-up rates and activation time between the two supplies can
cause current to flow in the I/O ESD protection circuitry. To
prevent damage to the ESD diode protection circuitry, Analog
Devices recommends including a bootstrap Schottky diode.
The bootstrap Schottky diode is connected between the core
and I/O power supplies, as shown in Figure 17. It protects the
ADSP-218xN processor from partially powering the I/O supply.
Including a Schottky diode will shorten the delay between the
supply ramps and thus prevent damage to the ESD diode pro-
tection circuitry. With this technique, if the core rail rises ahead
of the I/O rail, the Schottky diode pulls the I/O rail along with
the core rail.
DC INPUT
SOURCE
I/O VOLTAGE
REGULATOR
CORE
VOLTAGE
REGULATOR
VDDEXT
ADSP-218xN
VDDINT
Figure 17. Dual Voltage Schottky Diode
Table 13. Example Power Dissipation Calculation1
Parameters
Address
Data Output, WR
RD
CLKOUT, DMS
No. of Pins
7
9
1
2
× C (pF)
10
10
10
10
1 Total power dissipation for this example is PINT + 45.72 mW.
POWER DISSIPATION
To determine total power dissipation in a specific application,
the following equation should be applied for each output: C ؋
VDD2 ؋ f
where:
C = load capacitance.
f = output switching frequency.
Example: In an application where external data memory is used
and no other outputs are active, power dissipation is calculated
as follows:
Assumptions:
• External data memory is accessed every cycle with 50% of
the address pins switching.
• External data memory writes occur every other cycle with
50% of the data pins switching.
• Each address and data pin has a 10 pF total load at the pin.
• Application operates at VDDEXT = 3.3 V and tCK = 30 ns.
Total Power Dissipation = PINT + (C ؋VDDEXT2 ؋ f)
P INT = internal power dissipation from Figure 22 on Page 27.
(C ؋ VDDEXT2 ؋ f) is calculated for each output, as in the exam-
ple in Table 13.
× VDDEXT2 (V)
3.32
3.32
3.32
3.32
× f (MHz)
20.0
20.0
20.0
40.0
PD (mW)
15.25
19.59
2.18
8.70
45.72
Rev. A | Page 24 of 48 | August 2006
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