ADSP-2188NBSTZ-320 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-2188NBSTZ-320 Datasheet PDF : 48 Pages
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The EZ-ICE uses the EE (emulator enable) signal to take control
of the ADSP-218xN in the target system. This causes the proces-
sor to use its ERESET, EBR, and EBG pins instead of the RESET,
BR, and BG pins. The BG output is three-stated. These signals
do not need to be jumper-isolated in the system.
The EZ-ICE connects to the target system via a ribbon cable and
a 14-pin female plug. The female plug is plugged onto the 14-
pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 16. This connector must be added to the target board
design to use the EZ-ICE. Be sure to allow enough room in the
system to fit the EZ-ICE probe onto the 14-pin connector.
GND
EBG
EBR
KEY (NO PIN)
ELOUT
EE
RESET
1
2
3
4
5
6
7
8
؋
9
10
11
12
13
14
TOP VIEW
BG
BR
EINT
ELIN
ECLK
EMS
ERESET
Figure 16. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—Pin 7 must be removed from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1؋0.1 inch. The pin strip header must have at least
0.15 inch clearance on all sides to accept the EZ-ICE probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
Target Memory Interface
For the target system to be compatible with the EZ-ICE emula-
tor, it must comply with the following memory interface
guidelines:
Design the Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM), and Composite Memory
(CM) external interfaces to comply with worst-case device
timing requirements and switching characteristics as specified
in this data sheet. The performance of the EZ-ICE may
approach published worst-case specification for some memory
access timing requirements and switching characteristics.
Note: If the target does not meet the worst-case chip specifica-
tion for memory access parameters, the circuitry may not be
able to be emulated at the desired CLKIN frequency. Depending
on the severity of the specification violation, the system may be
ADSP-218xN
difficult to manufacture, as DSP components statistically vary in
switching characteristic and timing requirements, within pub-
lished limits.
Restriction: All memory strobe signals on the ADSP-218xN
(RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in the target
system must have 10 kΩ pull-up resistors connected when the
EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed
when the EZ-ICE is not being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals changes. Design the system to be compatible with
the following system interface signal changes introduced by the
EZ-ICE board:
• EZ-ICE emulation introduces an 8 ns propagation
delay between the target circuitry and the DSP on the
RESET signal.
• EZ-ICE emulation introduces an 8 ns propagation
delay between the target circuitry and the DSP on the BR
signal.
• EZ-ICE emulation ignores RESET and BR, when
single-stepping.
• EZ-ICE emulation ignores RESET and BR when in Emula-
tor Space (DSP halted).
• EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of
the DSP’s external memory bus only if bus grant (BG) is
asserted by the EZ-ICE board’s DSP.
ADDITIONAL INFORMATION
This data sheet provides a general overview of ADSP-218xN
series functionality. For additional information on the architec-
ture and instruction set of the processor, refer to the ADSP-218x
DSP Hardware Reference and the ADSP-218x DSP Instruction
Set Reference.
Rev. A | Page 17 of 48 | August 2006
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