MCP1811 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

MCP1811

Ultra-Low Quiescent Current LDO Regulator for Long-Life Battery-Powered Applications

Microchip Technology 

MCP1811A/11B/12A/12B

3.0 PIN DESCRIPTION

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP1811X/12X

4-Lead

1x1 mm UDFN

MCP1811X/12X

3-Lead

SOT-23/SC70

MCP1811X/12X

5-Lead

SOT-23/SC70

2

3

2

1

1

5

—

—

4

4

2

1

3

—

3

5

—

—

Symbol

Description

GND

VOUT

NC

VIN

SHDN

EP

Ground

Regulated Output Voltage VR

Not Connected Pins (should either be left

floated or connected to ground)

Input Voltage Supply

Shutdown Control Input (active-low); do not

leave this pin floating

Exposed Thermal Pad, connected to GND

3.1 Ground Pin (GND)

For optimal noise and Power Supply Rejection Ratio

(PSRR) performance, the GND pin of the LDO should

be tied to an electrically “quiet” ground circuit. The GND

pin of the LDO conducts only the ground current, so a

wider trace is not required. For powered applications

that have switching or noisy circuits, tie the GND pin to

the return of the output capacitor. Ground planes help

lower the inductance and voltage spikes caused by fast

transient load currents.

3.2 Regulated Output Voltage Pin

(VOUT)

The VOUT pin is the regulated output voltage VR of the

LDO. A minimum output capacitance of 1.0 μF

(MCP1811X) and 2.2 μF (MCP1812X) are required for

LDO stability. The MCP1811X/12X is stable with ceramic

capacitors. See Section 4.2 “Output Capacitor” for

output capacitor selection guidance.

3.3 Input Voltage Supply Pin (VIN)

Connect the input voltage source to VIN. If the input

voltage source is located several inches away from the

LDO or is a battery, it is recommended that an input

capacitor be used. A typical input capacitance value of

1 μF to 10 μF is sufficient for most applications (1 μF is

typical for MCP1811X and 2.2 μF is typical for

MCP1812X). The type of capacitor used is ceramic.

However, the low-ESR characteristics of the ceramic

capacitor will yield better noise and PSRR performance

at high frequency.

3.4 Shutdown Control Input (SHDN)

The SHDN input is used to turn the LDO output voltage

on and off. When the SHDN input is at a logic high level,

the LDO output voltage is enabled. When the SHDN

input is pulled to a logic low level, the LDO output voltage

is disabled (with output discharge for MCP1811A/12A).

When the SHDN input is pulled low, the LDO enters in a

low-current shutdown state, where the typical quiescent

current is 10 nA for MCP1811A/12A and 5 nA for

MCP1811B/12B.

 2018-2019 Microchip Technology Inc.

DS20006088B-page 19

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