ADUCM410 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADUCM410 Datasheet PDF : 35 Pages
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Data Sheet
ADuCM410
SPECIFICATIONS
AVDD = IOVDD0 = 2.85 V to 3.6 V, IOVDD1 = 1.2 V or 1.8 V, DVDD = 1.8 V to 3.6 V, VREF = 2.5 V for the internal reference, the
core frequency (fCORE) = 160 MHz, and TA = −40°C to +105°C, unless otherwise noted. HCLK is the high speed system clock.
Table 1.
Parameter
ADC CHANNEL SPECIFICATIONS
ADC Power-Up Time
Data Rate (fADC)
Resolution
Integral Nonlinearity
Differential Nonlinearity
DC Code Distribution1
ENDPOINT ERRORS
Offset Error
Offset Error Drift
Offset Error Drift Matching
Min
16
−4
−9.5
−9.5
−8
−8
−11.5
−15
−0.9
Typ
Max
5
2
±1
+3
±1
+6
±5
+8
±4
±5
±5
±8
±3
+12
±3
+8
±6
+11.5
±8
+15
±0.9
+1.5
±9
±5
±5
±5
−425
−770
±150
±200
+330
+830
−250
−415
−610
−1460
±150
±250
±200
±250
±4
±1
+225
+365
+555
+1375
Unit
μs
MSPS
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
μV
μV
μV
μV
μV
μV
μV/°C
μV/°C
Test Conditions/Comments
2.5 V internal reference
Voltage input to AINx, PGA off,
differential mode
Voltage input to AINx, PGA off, single-
ended mode
PGA voltage input to ADC, G = 2
G=4
G=6
G=8
G = 10
TIA input channels
TIA resistance (RTIA) = 250 Ω
RTIA = 750 Ω, 2 kΩ
RTIA = 5 kΩ
RTIA = 10 kΩ, 20 kΩ,100 kΩ
Differential and single-ended
Minimum and maximum range from
mean ADC codes for 1000 samples
ADC input = 2 V, single-ended mode,
fADC = 2 MSPS, PGA off
ADC input = 1 V, differential mode, fADC =
50 kSPS, PGA gain = 2, oversampling ratio
(OSR) = 8
ADC input = 200 mV, differential mode,
fADC = 50 kSPS, PGA gain = 10, OSR = 8
TIA mode, gain resistor = 100 kΩ, fADC =
25 kSPS, OSR = 4, input current = 10 μA
Voltage inputs only
PGA off
PGA channels; voltage input to ADC; G =
2, 4, 6, 8, 10; TIA input channels; all gain
settings; current converted to a voltage;
not production calibrated; user calibration
can remove this error
Gain resistor = 250 Ω, 750 Ω
Gain resistor = 2 kΩ
Gain resistor = 5 kΩ
Gain resistor = 10 kΩ, 20 kΩ,100 kΩ
PGA off
Matching compared to AIN0; for voltage
input channels, PGA off only
Rev. A | Page 5 of 35
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