ADUCM410 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADUCM410 Datasheet PDF : 35 Pages
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Data Sheet
Pin No. Mnemonic
F1
P1.5/MISO1/PWM3/PLAO11
F2
P1.6/MOSI1/PWM4/PLAO12
F3
P0.7/IRQ4/SDA2/COMPDIN1/PLAO5
F4
P3.2/PRTADDR2/PWMTRIP/PLAI14
F5
VDAC9/P5.1
F6
AIN8/COM0P
F7
ADCREFN
F8
ADCREFP
G1
P0.4/SCL0/SIN0/PLAO2
G2
P0.5/SDA0/SOUT0/PLAO3
G3
P0.6/IRQ3/SCL2/COMPDIN0/PLAO4
G4
P3.1/PRTADDR1/PWMSYNC/PLAI13
G5
VDAC11/P5.3
G6
AIN7/PADC23N/VDAC2
G7
AIN1
G8
AIN9/COM0N
H1
IOGND
ADuCM410
Type1
I/O
I/O
I/O
I/O
AO/I/O
AI
AO/AI
AO/AI
I/O
I/O
I/O
I/O
AO/I/O
AI
AI
AI
S
Description
Digital Input/Output Port 1.5 (P1.5).
SPI1 Master Input, Slave Output (MISO1).
PWM Output 3 (PWM3).
Output of PLA Element 11 (PLAO11).
Ball F1 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 1.6 (P1.6).
SPI1 Master Out, Slave Input (MOSI1).
PWM Output 4 (PWM4).
Output of PLA Element 12 (PLAO12).
Ball F2 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 0.7 (P0.7).
External Interrupt 4 (IRQ4).
I2C2 Serial Data (SDA2).
Comparator 1 Digital Input for Three-State (COMPDIN1).
Output of PLA Element 5 (PLAO5).
Digital Input/Output Port 3.2 (P3.2).
MDIO Port Address Bit 2 (PRTADDR2).
PWM Trip (PWMTRIP).
Input to PLA Element 14 (PLAI14).
Voltage DAC 9 Output (VDAC9).
Digital Input/Output Port 5.1 (P5.1).
Analog Input 8 (AIN8).
Comparator 0 VE Positive (COM0P).
Decoupling Capacitor Connection for ADC. Connect ADCREFN to AGND.
Decoupling Capacitor Connection for ADC Reference Buffer with 4.7 µF
Decoupling Capacitor.
Digital Input/Output Port 0.4 (P0.4).
I2C0 Serial Clock (SCL0).
UART0 Input (SIN0).
Output of PLA Element 2 (PLAO2).
Digital Input/Output Port 0.5 (P0.5).
I2C0 Serial Data (SDA0).
UART0 Output (SOUT0).
Output of PLA Element 3 (PLAO3).
Digital Input/Output Port 0.6 (P0.6).
External Interrupt 3 (IRQ3).
I2C2 Serial Clock (SCL2).
Comparator 0 Digital Input for Three-State (COMPDIN0).
Output of PLA Element 4 (PLAO4).
Digital Input/Output Port 3.1 (P3.1).
MDIO Port Address Bit 1 (PRTADDR1).
PWM Synchronization (PWMSYNC).
Input to PLA Element 13 (PLAI13).
Voltage DAC 11 Output (VDAC11).
Digital Input/Output Port 5.1 (P5.3).
Analog Input 7 (AIN7).
PGA Channel 2/PGA Channel 3 Negative (PADC23N).
Voltage DAC 2 Output (VDAC2).
Analog Input 1.
Analog Input 9 (AIN9).
Comparator 0 VE Negative (COM0N).
Ground for Digital Inputs/Outputs.
Rev. A | Page 27 of 35
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