ST72361XX-AUTO View Datasheet(PDF) - STMicroelectronics
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Description
Manufacturer
ST72361XX-AUTO
STMicroelectronics
ST72361XX-AUTO Datasheet PDF : 279 Pages
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ST72361xx-Auto
Interrupts
Note:
if the corresponding enable bit is set in the peripheral control register.
The general sequence for clearing an interrupt is based on an access to the status register
followed by a read or write to an associated register.
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for
being serviced) will therefore be lost if the clear sequence is executed.
6.3
Note:
Interrupts and low power modes
All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the HALT modes (see
column “Exit from HALT” in “Interrupt Mapping” table). When several pending interrupts are
present while exiting HALT mode, the first one serviced can only be an interrupt with exit
from HALT mode capability and it is selected through the same decision process shown in
Figure 18.
If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced after the first one serviced.
6.4
Concurrent & nested management
The following Figure 19 and Figure 20 show two different interrupt management modes. The
first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the
nested mode in Figure 20. The interrupt hardware priority is given in this order from the
lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for
each interrupt.
Warning: A stack overflow may occur without notifying the software of
the failure.
Figure 19. Concurrent interrupt management
TLI
IT0
IT1
IT1
IT2
IT3
RIM
MAIN
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SOFTWARE
PRIORITY
I1
I0
LEVEL
IT4
MAIN
10
3
11
3
11
3
11
3
11
3
11
3
11
3/0
Doc ID 12468 Rev 3
51/279
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