ST72361xx-Auto
Supply, reset and clock management
5.5.5
The device RESET pin acts as an output that is pulled low when VDD < VIT+ (rising edge) or
VDD < VIT- (falling edge) as shown in Figure 14.
The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.
Internal watchdog reset
The RESET sequence generated by a internal Watchdog counter overflow is shown in
Figure 14.
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least tw(RSTL)out.
Figure 14. Reset sequences
VDD
VIT+(LVD)
VIT-(LVD)
RUN
LVD
RESET
ACTIVE PHASE
RUN
EXTERNAL
RESET
ACTIVE
PHASE
RUN
WATCHDOG
RESET
ACTIVE
PHASE
RUN
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
th(RSTL)in
tw(RSTL)out
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU)
VECTOR FETCH
5.6
5.6.1
System integrity management (SI)
The System Integrity Management block contains the Low Voltage Detector (LVD) and
Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.
Low voltage detector (LVD)
The Low Voltage Detector function (LVD) generates a static reset when the VDD supply
voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well
as the power-down keeping the ST7 in reset.
The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
current on the supply (hysteresis).
The LVD reset circuitry generates a reset when VDD is below:
● VIT+(LVD) when VDD is rising
● VIT-(LVD) when VDD is falling
Doc ID 12468 Rev 3
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