PM8313-RI View Datasheet(PDF) - PMC-Sierra

Part Name

Description

Manufacturer

PM8313-RI

M13 MULTIPLEXER

PMC-Sierra 

DATA SHEET

PMC-920702

ISSUE 5

PM8313 D3MX

M13 MULTIPLEXER

When enabled for C-bit parity operation, both the far end alarm and control

channel and the path maintenance data link are extracted and serialized at 9.4

kbit/s and 28.2 kbit/s, respectively. Codes in the extracted far end alarm and

control (FEAC) channel may be detected with the Bit-Oriented Code Detector

(RBOC). HDLC messages in the extracted path maintenance data link may be

received with the Data Link Receiver (RFDL).

The FRMR may be configured for C-bit parity mode or left in M23 mode. When

C-bit parity mode is not enabled, outputs relating to C-bit parity features are

forced to an inactive state. The FRMR, however, provides an indication of

whether the C-bit parity application is present or absent, independent of how it is

configured.

The FRMR may be configured to generate interrupts on error events or status

changes. All sources of interrupts can be masked or acknowledged via internal

registers. Internal registers are also used to configure the FRMR. Access to

these registers is via a generic microprocessor bus.

Under DS3 AIS, LOF or LOS conditions, the M23 and M12 Multiplexers can

receive data which corresponds to a continuous C-bit stuff ratio of between 0 and

100%. At the extremes of the stuff ratio (i.e. 0% and 100%) the recovered

DS1/E1 tributary clocks will exceed their nominal value by up to +/-1750 ppm.

This tributary frequency excursion could pose a problem for downstream circuitry

in some applications.

8.2 DS3 Performance Monitor

The DS3 Performance Monitor (PMON) Block interfaces directly with the T3

Framer (FRMR) to accumulate line code violation (LCV) events, excessive zeros

occurrences (EXZS), P-bit parity error (PERR) events, C-bit parity error (CPERR)

events, far end block error (FEBE) events, and framing bit error (FERR) events in

counters over intervals which are defined by successive microprocessor writes to

a PMON counter register location. Each counter saturates at a specific value.

Due to the off-line nature of the T3 Framer, PMON continues to accumulate error

events even while the FRMR is indicating OOF.

When a microprocessor write to a PMON count register is performed, a transfer

clock signal is generated. This transfer clock causes the PMON block to transfer

the current counter values into holding registers and reset the counters to begin

accumulating error events for the next interval. The counters are reset in such a

manner that error events occurring during the reset period are not missed.

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