DATA SHEET
PMC-920702
ISSUE 5
PM8313 D3MX
M13 MULTIPLEXER
Pin Name
RFERF
Type Pin No. Function
Output
23 The receive far end receive failure (RFERF)
signal reflects the value of the internal FERF
state buffered by two M-frames. Internally,
FERF is set high when both X-bits (X1 and X2)
are received as logic 0 in the current M-frame;
FERF is set low when both X-bits are received
as logic 1. FERF remains in its previous state
when X1 • X2 in the current M-frame. The
RFERF output latency provides a better than
99.99% chance of freezing (i.e. holding RFERF
in its previous state) upon a valid state value
during the occurrence of an out of frame.
RFERF is updated once per M-frame on the
falling edge of ROHCLK.
18