AD5260BRU50-REEL7 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD5260BRU50-REEL7 Datasheet PDF : 20 Pages
| |||
AD5260/AD5262
Parameter
Symbol
Conditions
Min Typ Max Unit
INTERFACE TIMING CHARACTERISTICS apply to all parts6, 12
Clock Frequency
fCLK
25 MHz
Input Clock Pulsewidth
tCH, tCL
Clock level high or low
20
ns
Data Setup Time
tDS
10
ns
Data Hold Time
tDH
10
ns
CLK to SDO Propagation Delay13
tPD
RL = 1 kΩ, CL < 20pF
1
160 ns
CS Setup Time
tCSS
5
ns
CS High Pulsewidth
tCSW
20
ns
Reset Pulsewidth
tRS
CLK Fall to CS Rise Hold Time
tCSH
CS Rise to Clock Rise Setup
tCS1
50
ns
0
ns
10
ns
NOTES
The AD5260/AD5262 contains 1,968 transistors. Die Size: 89 mil. × 105 mil. 9,345 sq. mil.
1Typicals represent average readings at 25°C and VDD = +5 V, VSS = –5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = +5 V, VSS = –5 V.
3 VAB = VDD, Wiper (VW) = No connect.
4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V DD and VB = 0V. DNL
specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.
5Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6Guaranteed by design and not subject to production test.
7Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.
8Worst-case supply current consumed when input all logic-input levels set at 2.4 V, standard characteristic of CMOS logic.
9 PDISS is calculated from (IDD ϫ VDD). CMOS logic level inputs result in minimum power dissipation.
10 All dynamic characteristics use VDD = +5 V, VSS = –5 V, VL = +5 V.
11Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
12 See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using VL = 5 V.
13 Propagation delay depends on value of VDD, RL, and CL.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +15 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
AX – BX, AX – WX, BX – WX
Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Digital Inputs and Output Voltage to GND . . . . . . . 0 V, 7 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Thermal Resistance3 θJA
TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance setting.
3Package Power Dissipation = (TJ MAX – TA)/ θJA
REV. 0
–3–
|
|
Share Link: 