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SLX24C08/16/P View Datasheet(PDF) - Siemens AG

Part NameDescriptionManufacturer
SLX24C08/16/P 8/16 Kbit (1024/2048 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus and Page Protection Mode™ Siemens
Siemens AG Siemens
SLX24C08/16/P Datasheet PDF : 27 Pages
First Prev 21 22 23 24 25 26 27
SLx 24C08/16/P
The control byte CTx is followed by 16 parameter bytes identical to the 16 data bytes of
the page to be protected or unprotected. The data of the first entered byte must be
identical to the data byte stored at the lowest address of the current page. The other 15
bytes have to be identical to the bytes stored in ascending address order within the same
page.
A successful verification of each byte is indicated by the EEPROM by pulling the SDA
line to low (acknowledge ACK).
After verification of the last byte, the bit programming procedure is initiated by the STOP
condition. Programming is started only if all 128 bits of a page have been verified
successfully. If bit programming has taken place, the address counter points to the
uppermost address of the respective page. The write or erase cycle is finished latest
after 4 ms. Acknowledge polling may be used for speed enhancement in order to
indicate the end of the write or erase cycle (refer to chapter 5.3 Acknowledge Polling).
Semiconductor Group
21
1998-07-27
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