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SLA24C08-D-3/P View Datasheet(PDF) - Siemens AG

Part NameDescriptionManufacturer
SLA24C08-D-3/P 8/16 Kbit (1024/2048 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus and Page Protection Mode™ Siemens
Siemens AG Siemens
SLA24C08-D-3/P Datasheet PDF : 27 Pages
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SLx 24C08/16/P
7.1 Protection Bit Handling
The bits of the protection memory can be addressed directly for reading or programming.
A protection bit address corresponds to the lowest address within the respective page
(A4 to A9 or A10, A0 to A3 = zero). The status of each protection bit is sensed internally.
A written state (“0”) prevents programming in the associated page. If an already
protected memory page is accidentally addressed for programming, the programming
procedure is suppressed.
The conventional I2C-Bus protocol allows data bytes to be read and programmed only.
Therefore an independent instruction sequence for addressing and manipulation of
protection bits is implemented. For protection bit instructions, the command byte CSW
with its preceding START condition followed by the associated control byte has to be
entered twice (figures 15 through 17). The first command byte CSW (with A8 to A9 or
A10) is followed by the control byte EEA with the bit/page address A0 through A3 always
at zero. The second CSW is required for entering a control byte CTx for protection bit
manipulation. The three control bytes for read, write or erase of a protection bit are listed
below (table 3):
Table 3
Control Byte for Protection Bit Manipulation
b7 b6 b5 b4 b3 b2 b1 b0
x x x x x x 0 0 Protection bit read
x x x x x x 0 1 Protection bit write
x x x x x x 1 1 Protection bit erase
Semiconductor Group
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