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SLA24C08-D-3/P View Datasheet(PDF) - Siemens AG

Part NameDescriptionManufacturer
SLA24C08-D-3/P 8/16 Kbit (1024/2048 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus and Page Protection Mode™ Siemens
Siemens AG Siemens
SLA24C08-D-3/P Datasheet PDF : 27 Pages
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SLx 24C08/16/P
7
Page Protection ModeTM
Each page (16 bytes) in the Data Memory can be protected against unintended data
changes by an associated protection bit. The protection bit memory consists of an
additional EEPROM of 64/128 bits (figure 14).
Data in the Data Memory can be modified only if the assigned protection bit is erased
(logical state “1”). After writing the data bytes to a page, the protection is achieved by
writing the associated protection bit (logical state “0”). Further changes in the data in a
protected page is possible only after erasing the protection bit.
Page 0
Page 1
Page 2
Page 3
...
Page n 0 1 2 3
Data Memory Area
...
...
Byte
0
1
2
3
...
15 n
Bit
IED02272
Figure 14
Data Page and Assigned Protection Memory
A special procedure to write or erase a protection bit guarantees proper activation or
deactivation respectively of page protection. For protection bit write or erase, all 16 data
bytes of the respective page have to be entered for a second time. The data then are
compared internally with the data to be protected, and in case of identity the protection
bit is written or erased respectively.
Semiconductor Group
18
1998-07-27
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