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SLA24C08-D-3/P View Datasheet(PDF) - Siemens AG

Part NameDescriptionManufacturer
SLA24C08-D-3/P 8/16 Kbit (1024/2048 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus and Page Protection Mode™ Siemens
Siemens AG Siemens
SLA24C08-D-3/P Datasheet PDF : 27 Pages
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SLx 24C08/16/P
5.3 Acknowledge Polling
During the erase/write cycle the EEPROM will not respond to a new command byte until
the internal write procedure is completed. At the end of active programming the chip
returns to the standby mode and the last entered EEPROM byte remains addressed by
the address counter. To determine the end of the internal erase/write cycle acknowledge
polling can be initiated by the master by sending a START condition followed by a
command byte CSR or CSW (read with b0 = 1 or write with b0 = 0). If the internal erase/
write cycle is not completed, the device will not acknowledge the transmission. If the
internal erase/write cycle is completed, the device acknowledges the received command
byte and the protocol activities can continue.
Internal Programming
Send Start
Send CS-Byte
Next Operation
Figure 9
Flow Chart “Acknowledge Polling”
Semiconductor Group
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