ST72324J2-AUTO View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72324J2-AUTO
STMicroelectronics
ST72324J2-AUTO Datasheet PDF : 194 Pages
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ST72324xx-Auto
Interrupts
Note:
peripheral control register. The general sequence for clearing an interrupt is based on an
access to the status register followed by a read or write to an associated register.
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be
serviced) is therefore lost if the clear sequence is executed.
7.3
Interrupts and low power modes
All interrupts allow the processor to exit the Wait low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the Halt modes (see
column Exit from HALT in Table 25: Interrupt mapping). When several pending interrupts are
present while exiting Halt mode, the first one serviced can only be an interrupt with Exit from
t(s) Note:
t(s) - Obsolete Produc 7.4
Halt mode capability and it is selected through the same decision process shown in
Figure 17.
If an interrupt, that is not able to exit from Halt mode, is pending with the highest priority
when exiting Halt mode, this interrupt is serviced after the first one serviced.
Concurrent and nested management
Figure 18 and Figure 19 show two different interrupt management modes. The first is called
concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode
in Figure 19. The interrupt hardware priority is given in order from the lowest to the highest
as follows: MAIN, IT4, IT3, IT2, IT1, IT0. Software priority is given for each interrupt.
Warning: A stack overflow may occur without notifying the software of
the failure.
duc Figure 18. Concurrent interrupt management
lete Pro TRAP
o IT0
bs IT1
IT1
O IT2
Software
priority
I1
I0
level
3
11
3
11
3
11
3
11
IT3
3
11
RIM
IT4
3
11
Main
11/10
Main
3/0
10
Doc ID 13841 Rev 1
45/193
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