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GS880E18AT-133 View Datasheet(PDF) - Giga Semiconductor

Part NameDescriptionManufacturer
GS880E18AT-133 512K x 18, 256K x 32, 256K x 36 9Mb Synchronous Burst SRAMs GSI
Giga Semiconductor GSI
GS880E18AT-133 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
TQFP Pin Description
Symbol
A0, A1
An
DQA
DQB
DQC
DQD
NC
BW
BA, BB, BC, BD
CK
GW
E1, E3
E2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
VDD
VSS
VDDQ
Type
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
GS880E18/32/36AT-250/225/200/166/150/133
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Data Input and Output pin
No Connect
Byte WriteWrites all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Clock Input Signal; active high
Global Write EnableWrites all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.03 11/2004
5/24
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
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