ADSP-2171KST-104 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-2171KST-104 Datasheet PDF : 52 Pages
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ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173
CAPACITIVE LOADING
Figures 35 and 36 show the capacitive loading characteristics of
the ADSP-2173.
28
24
VDD = 3.3 V
20
16
tDECAY, is dependent on the capacitative load, CL, and the cur-
rent load, iL, on the output pin. It can be approximated by the
following equation:
from which
tDECAY
=
CL
• 0.5V
iL
tDIS = tMEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
INPUT
VDD
2
12
8
25
50
75
100
125
150
CL – pF
Figure 35. Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
+14
+12
+10
+8
+4
+2
NOMINAL
-2
25
50
75
100
125
150
CL – pF
Figure 36. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured out-
put high or low voltage to a high impedance state. The output
disable time (tDIS) is the difference of tMEASURED and tDECAY, as
shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low volt-
age level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
VDD
OUTPUT
2
Figure 37. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start driv-
ing. The output enable time (tENA) is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
REFERENCE
SIGNAL
tMEASURED
VOH tDIS
(MEASURED)
OUTPUT
VOL
(MEASURED)
VOH (MEASURED) – 0.5V
VOL (MEASURED) +0.5V
tDECAY
tENA
2.0V
1.0V
VOH
(MEASURED)
VOL
(MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
Figure 38. Output Enable/Disable
IOL
TO
OUTPUT
VDD
PIN
2
50pF
IOH
Figure 39. Equivalent Device Loading for AC Measure-
ments (Including All Fixtures)
–44–
REV. A
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