ADSP-2171KST-104 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-2171KST-104 Datasheet PDF : 52 Pages
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ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173
Parameter
Min
Max
Unit
Bus Request/Grant
Timing Requirement:
tBH
BR Hold after CLKOUT High1
0.25tCK + 2
ns
tBS
BR Setup before CLKOUT Low1
0.25tCK + 22
ns
Switching Characteristic:
tSD
tSDB
tSE
tSEC
tSDBH
tSEH
CLKOUT High to DMS, PMS, BMS,
RD, WR Disable
DMS, PMS, BMS, RD, WR
Disable to BG Low
BG High to DMS, PMS, BMS,
RD, WR Enable
DMS, PMS, BMS, RD, WR
Enable to CLKOUT High
DMS, PMS, BMS, RD, WR
Disable to BGH Low2
BGH High to DMS, PMS, BMS,
RD, WR Enable2
0
0
0.25tCK – 10
0
0
0.25tCK + 16
ns
ns
ns
ns
ns
ns
NOTES
1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized
on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
2BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR
BG
BGH
tSD
tSEC
tSDB
tSE
tSDBH
tSEH
Figure 26. Bus Request–Bus Grant
REV. A
–35–
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