AD5757
Data Sheet
Slew Rate Control Register
This register is used to program the slew rate control for the
selected DAC channel. The slew rate control is enabled/
disabled and programmed on a per channel basis.See Table 25
and the Digital Slew Rate Control section formore information.
READBACK OPERATION
Readback mode is invoked by setting the R/W bit to 1 in the serial
input register write. See Table 26 and Table 27 for the bits
associated with a readback operation. The DUT_AD1 bit and
DUT_AD0 bit, in association with bits RD[4:0], select the
register to be read. The remaining data bits in the write
sequence are don’t cares.
During the next SPI transfer (see Figure 4), either a NOP or a
request to read anotherregister must be issued. Meanwhile the
SDO returns 24 bits, the 8 MSBs are don’t cares, and the 16
LSBs contain the data from the addressed register. The SDOis
loaded on each rising edge of SCLK and read on each falling
edge of SCLK.
If PEC is enabled, the SDO returns 32 bits (Figure 5), with 8
CRC bits appended to the data readback. There must be no
activity on SCLK between read commandand NOP command,
or an incorrect PEC may be read back.
Readback Example
To read back the gain register of Device 1, Channel A on the
AD5757, implement the following sequence:
1. Write 0xA80000 to the AD5757 input register. This
configures the AD5757 Device Address 1 for readmode
with the gain register of Channel A selected. All the data
bits, [D15:D0], are don’t cares.
2. Follow with another read commandor a no operation
command (0x3CE000). During this command, the data
from the Channel A gain register is clocked out on the
SDO line.
Table 25. Programming the Slew Rate Control Register
D15
D14
D13
D12
0
0
0
SREN
1 X = don’t care.
D11 to D7
X1
D6 to D3
SR_CLOCK
D2 to D0
SR_STEP
Table 26. Input Shift Register Contents for a Read Operation
D23
D22
D21
D20
D19
R/W
DUT_AD1
DUT_AD0 RD4
RD3
1 X = don’t care.
D18
D17
RD2
RD1
D16
D15 to D0
RD0
X1
Table 27. Read Address Decoding
RD4
RD3
RD2
RD1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
RD0
Function
0
Read DAC A data register
1
Read DAC B data register
0
Read DAC C data register
1
Read DAC D data register
0
Read DAC A control register
1
Read DAC B control register
0
Read DAC C control register
1
Read DAC D control register
0
Read DAC A gain register
1
Read DAC B gain register
0
Read DAC C gain register
1
Read DAC D gain register
0
Read DACA offset register
1
Read DAC B offset register
0
Read DAC C offset register
1
Read DAC D offset register
0
Clear DAC A code register
1
Clear DAC B code register
0
Clear DAC C code register
1
Clear DAC D code register
0
DAC A slew rate control register
1
DAC B slew rate control register
0
DAC C slew rate control register
1
DAC D slew rate control register
0
Read status register
1
Read main control register
0
Read dc-to-dc control register
Rev. G | Page 32 of 45