Data Sheet
CONTROL REGISTERS
When writing to a control register, the formatshown in Table 15
must be used. See Table 8 for information on the configuration
of Bit D23 to Bit D16. The controlregistersare addressed by setting
the DREG[2:0] bits to 111 and then setting the CREG[2:0] bits
to the appropriate decode addressfor that register, according to
Table 16. These CREG bits select among the various control
registers.
AD5757
Main Control Register
The main control register options are shown in Table 17 and
Table 18. See the Device Features section formore information
on the featurescontrolled by the main Control Register.
Table 15. Writing to a Control Register
MSB
D23 D22
D21
D20 D19 D18 D17
R/W DUT_AD1 DUT_AD0 1
1
1
DAC_AD1
D16
DAC_AD0
D15
CREG2
D14
CREG1
D13
CREG0
LSB
D12 to D0
Data
Table 16. Register Access Decode
CREG2 (D15)
CREG1 (D14)
0
0
0
0
0
1
0
1
1
0
CREG0 (D13)
0
1
0
1
0
Function
Slew rate control register (one per channel)
Main control register
DAC control register (one per channel)
DC-to-dc control register
Software register
Table 17. Programming the Main Control Register
MSB
D15 D14 D13 D12 D11
D10 D9 D8 D7 D6
0
0
1
0
STATREAD EWD WD1 WD0 X1
X1
D5
D4
OUTEN_ALL DCDC_ALL
LSB
D3 to D0
X1
1 X = don’t care.
Table 18. Main Control Register Functions
Bit
Description
STATREAD
Enable status readback during a write. See the Device Features section.
STATREAD = 1, enable.
STATREAD = 0, disable (default).
EWD
Enable watchdog timer. See the Device Features section for more information.
EWD = 1, enable watchdog.
EWD = 0, disable watchdog (default).
WD1, WD0
Timeout select bits. Used to select the timeout period for the watchdog timer.
WD1
WD0
Timeout Period (ms)
0
0
5
0
1
10
1
0
100
1
1
200
OUTEN_ALL Enables the output on all four DACs simultaneously.
Do not use the OUTEN_ALL bit when using the OUTEN bit in the DAC control register.
DCDC_ALL
When set, powers up the dc-to-dc converter on all four channels simultaneously.
To power down the dc-to-dc converters, all channel outputs must first be disabled.
Do not use the DCDC_ALL bit when using the DC_DC bit in the DAC control register.
Rev. G | Page 29 of 45