MAX11044 View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX11044 Datasheet PDF : 28 Pages
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MAX11044/MAX11044B/MAX11045/MAX11045B/
MAX11046/MAX11046B/MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
MAX11044/
MAX11044B
(TQFN-EP)
1
2
3
4
5
6
7, 21, 50
8, 20, 51
9
10
11
12
13
14
15
16
PIN
MAX11045/
MAX11045B
(TQFN-EP)
1
2
3
4
5
6
7, 21, 50
8, 20, 51
9
10
11
12
13
14
15
16
MAX11046/
MAX11046B
(TQFN-EP)
1
2
3
4
5
6
7, 21, 50
8, 20, 51
9
10
11
12
13
14
15
16
17
17
17
18
18
18
19
19
19
22, 28, 35,
43, 49
22, 28, 35,
43, 49
22, 28, 35,
43, 49
23, 27, 33, 38,
44, 48
23, 27, 33, 38,
44, 48
23, 27, 33, 38,
44, 48
Pin Description
NAME
FUNCTION
DB13
DB12
DB11
DB10
DB9
DB8
DGND
DVDD
DB7
DB6
DB5
DB4
DB3/CR3
DB2/CR2
DB1/CR1
DB0/CR0
EOC
CONVST
SHDN
RDC
AGNDS
16-Bit Parallel Data Bus Digital Output Bit 13
16-Bit Parallel Data Bus Digital Output Bit 12
16-Bit Parallel Data Bus Digital Output Bit 11
16-Bit Parallel Data Bus Digital Output Bit 10
16-Bit Parallel Data Bus Digital Output Bit 9
16-Bit Parallel Data Bus Digital Output Bit 8
Digital Ground
Digital Supply. Bypass to DGND with a 0.1μF capacitor
at each DVDD input.
16-Bit Parallel Data Bus Digital Output Bit 7
16-Bit Parallel Data Bus Digital Output Bit 6
16-Bit Parallel Data Bus Digital Output Bit 5
16-Bit Parallel Data Bus Digital Output Bit 4
16-Bit Parallel Data Bus Digital Output Bit 3/
Configuration Register Input Bit 3
16-Bit Parallel Data Bus Digital Output Bit 2/
Configuration Register Input Bit 2
16-Bit Parallel Data Bus Digital Output Bit 1/
Configuration Register Input Bit 1
16-Bit Parallel Data Bus Digital Output Bit 0/
Configuration Register Input Bit 0
Active-Low End-of-Conversion Output. EOC goes low
when conversion is completed. EOC goes high when a
conversion is initiated.
Convert Start Input. Rising edge of CONVST ends
sample and starts a conversion on the captured sample.
The ADC is in acquisition mode when CONVST is low
and CONVST mode = 0.
Shutdown Input. If SHDN is held high, the entire device
will enter and stay in a low-current state. Contents of
the configuration register are not lost when in the
shutdown mode.
Reference Buffer Decoupling. Connect all RDC outputs
together. Bypass to AGND with at least an 80μF total
capacitance. See the Layout, Grounding, and Bypassing
section.
Signal Ground. Connect all AGND and AGNDS inputs
together on PCB.
10
Maxim Integrated
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