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U630H64DK25 查看數據表(PDF) - Zentrum Mikroelektronik Dresden AG

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U630H64DK25 HardStore 8K x 8 nvSRAM ZMD
Zentrum Mikroelektronik Dresden AG ZMD
U630H64DK25 Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
U630H64
Write Cycle #1: W-controlledj
Ai
E
W
DQi
Input
DQi
Output
12
tcW
Address Valid
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
17
tsu(E)
16
tsu(A-WH)
21
AAAAAAAAAAAAAAAAAAAAAAAAAAAAtAAAAh(AAAAA)AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
15AAAAAAAAAAAAAAAAAAAAAAAAAAAA
tsu(A)
13
tw(W)
19
tsu(D)
20
th(D)
Input Data
Valid
22
tdis(W)
Previous Data
23
ten(W)
High Impedance
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Write Cycle #2: E-controlledj
Ai
15
tsu(A)
E
W
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
DQi
Input
DQi
Output
12
tcW
Address Valid
18
21
tw(E)
th(A )
14
tsu(W)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
19
tsu(D)
20
th(D)
Input Data
Valid
High Impedance
undefined AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
L- to H-level AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
H- to L-level AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
j: E or W and NE must be > VIH during address transitions.
6
December 12, 1997
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