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U630H64DK25 查看數據表(PDF) - Zentrum Mikroelektronik Dresden AG

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U630H64DK25 HardStore 8K x 8 nvSRAM ZMD
Zentrum Mikroelektronik Dresden AG ZMD
U630H64DK25 Datasheet PDF : 14 Pages
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U630H64
HardStore 8K x 8 nvSRAM
Features
F High-performance CMOS nonvo-
latile static RAM 8192 x 8 bits
F 25, 35 and 45 ns Access Times
F 12, 20 and 25 ns Output Enable
F Access Times
Hardware STORE Initiation
(STORE Cycle Time < 10 ms)
F Automatic STORE Timing
F 105 STORE cycles to EEPROM
F 10 years data retention in
EEPROM
F Automatic RECALL on Power Up
F Hardware RECALL Initiation
F (RECALL Cycle Time < 20 µs)
Unlimited RECALL cycles from
F EEPROM
Unlimited Read and Write to
SRAM
F Single 5 V ± 10 % Operation
F Operating temperature ranges:
0 to 70 °C
F -40 to 85 °C
CECC 90000 Quality Standard
F ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code
F Numbers)
Packages: PDIP28 (300 mil)
SOP28 (330 mil)
Description
The U630H64 has two separate
modes of operation: SRAM mode
and nonvolatile mode, determined
by the state of the NE pin.
In SRAM mode, the memory ope-
rates as an ordinary static RAM. In
nonvolatile operation, data is trans-
ferred in parallel from SRAM to
EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
The U630H64 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through the state of the NE pin.
The U630H64 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
NE
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7 PDIP 22
8 SOP 21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W
n.c.
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
December 12, 1997
Pin Description
Signal Name
A0 - A12
DQ0 - DQ7
E
G
W
NE
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Nonvolatile Enable
Power Supply Voltage
Ground
1
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